Extreme silicon thinning for back side power delivery network: Si thinning stopping on scaled SiGe etch stop layer

IF 2.6 4区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC
Farid Sebaai , Roger Loo , Anne Jourdain , Eric Beyne , Hikaru Kawarazaki , Teppei Nakano , Efrain Altamirano Sanchez
{"title":"Extreme silicon thinning for back side power delivery network: Si thinning stopping on scaled SiGe etch stop layer","authors":"Farid Sebaai ,&nbsp;Roger Loo ,&nbsp;Anne Jourdain ,&nbsp;Eric Beyne ,&nbsp;Hikaru Kawarazaki ,&nbsp;Teppei Nakano ,&nbsp;Efrain Altamirano Sanchez","doi":"10.1016/j.mee.2024.112246","DOIUrl":null,"url":null,"abstract":"<div><p>This paper discusses the challenges relative to the silicon thinning which allows the back side power delivery integration (BSPDN). The back side silicon thinning stopping on a thin Si<sub>0.75</sub>Ge<sub>0.25</sub> etch stop layer (ESL) has been investigated as it represents an alternative to the use of SOI wafers. Etch stop layers using 10 nm Si<sub>0.75</sub>Ge<sub>0.25</sub> or 10 nm Si<sub>0.75</sub>Ge<sub>0.25</sub> boron doped (Si<sub>0.75</sub>Ge<sub>0.25</sub>:B) have been studied for which different thinning process sequences were considered. All the considered thinning sequences are terminated with a diluted ammonia (NH<sub>4</sub>OH) process which provides the selectivity towards the ESL. Considering a 10 nm Si<sub>0.75</sub>Ge<sub>0.25</sub>:B as an ESL considerably increases the selectivity of the last diluted NH<sub>4</sub>OH silicon etching step. It nevertheless induces a risk of device poisoning caused by the diffusion of boron. Considering a 10 nm Si<sub>0.75</sub>Ge<sub>0.25</sub> as an ESL has been then demonstrated using different thinning process sequences. Those alternative thinning sequences were optimized with respect to the silicon removal within wafer uniformity.</p></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"294 ","pages":"Article 112246"},"PeriodicalIF":2.6000,"publicationDate":"2024-07-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Microelectronic Engineering","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S0167931724001151","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0

Abstract

This paper discusses the challenges relative to the silicon thinning which allows the back side power delivery integration (BSPDN). The back side silicon thinning stopping on a thin Si0.75Ge0.25 etch stop layer (ESL) has been investigated as it represents an alternative to the use of SOI wafers. Etch stop layers using 10 nm Si0.75Ge0.25 or 10 nm Si0.75Ge0.25 boron doped (Si0.75Ge0.25:B) have been studied for which different thinning process sequences were considered. All the considered thinning sequences are terminated with a diluted ammonia (NH4OH) process which provides the selectivity towards the ESL. Considering a 10 nm Si0.75Ge0.25:B as an ESL considerably increases the selectivity of the last diluted NH4OH silicon etching step. It nevertheless induces a risk of device poisoning caused by the diffusion of boron. Considering a 10 nm Si0.75Ge0.25 as an ESL has been then demonstrated using different thinning process sequences. Those alternative thinning sequences were optimized with respect to the silicon removal within wafer uniformity.

用于背面输电网络的极端硅减薄:在按比例硅锗蚀刻停止层上停止硅减薄
本文讨论了实现背面功率传输集成(BSPDN)的硅减薄所面临的挑战。本文研究了在薄硅锗蚀刻停止层(ESL)上停止背面硅减薄的问题,因为这代表了使用 SOI 晶圆的一种替代方法。对使用 10 nm SiGe 或 10 nm 掺硼 SiGe(SiGe:B)的蚀刻阻挡层进行了研究,并考虑了不同的减薄工艺顺序。所有考虑过的减薄顺序都是以稀释氨水 (NHOH) 工艺终止,该工艺提供了对 ESL 的选择性。将 10 nm SiGe:B 作为 ESL 可大大提高最后一个稀释 NHOH 硅蚀刻步骤的选择性。然而,硼的扩散会导致器件中毒的风险。将 10 nm SiGe 作为 ESL 后,使用不同的稀化工艺顺序进行了验证。在硅片均匀性的前提下,对这些不同的薄化顺序进行了硅去除优化。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
Microelectronic Engineering
Microelectronic Engineering 工程技术-工程:电子与电气
CiteScore
5.30
自引率
4.30%
发文量
131
审稿时长
29 days
期刊介绍: Microelectronic Engineering is the premier nanoprocessing, and nanotechnology journal focusing on fabrication of electronic, photonic, bioelectronic, electromechanic and fluidic devices and systems, and their applications in the broad areas of electronics, photonics, energy, life sciences, and environment. It covers also the expanding interdisciplinary field of "more than Moore" and "beyond Moore" integrated nanoelectronics / photonics and micro-/nano-/bio-systems. Through its unique mixture of peer-reviewed articles, reviews, accelerated publications, short and Technical notes, and the latest research news on key developments, Microelectronic Engineering provides comprehensive coverage of this exciting, interdisciplinary and dynamic new field for researchers in academia and professionals in industry.
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信