Electron trapping in HfO2 layer deposited over a HF last treated silicon substrate

Electron trapping in HfO₂-based MOS structures was studied through pulsed capacitance-voltage (C-V) technique. 10 nm HfO₂ layer was deposited by atomic layer deposition over a HF last treated Si substrate. The C-V curves were observed to shift to positive voltages driven by the positive applied voltage along the pulses, consistent with electron trapping due to tunneling transitions between the substrate and pre-existing defects within the oxide and the subsequent lattice relaxation through electron-phonon interaction. The dependences of the voltage shift for a given capacitance value (ΔV_C) with stress bias and time, allowed to distinguish two mechanisms. An initial trapping process occurs for times shorter than the microsecond, probably associated with a thin non-stoichiometric SiO_x interfacial layer, which is followed by a trapping process that starts after tens of μs and progressively slowed down, associated with traps within the HfO₂ layer. Numerical simulations yield for the HfO₂ traps an energy of 1.3 eV below the conduction band edge, decreasing exponentially with the distance from the Si interface with a characteristic length of 1.7 nm; and phonon and relaxation energies of 50 meV and 1 eV, respectively. These physical parameters are consistent with previous reports of electron trapping in HfO₂ layers deposited on a controlled interfacial layer, suggesting that trapping properties of defects inside the HfO₂ layer are insensitive to the treatment of the Si surface before HfO₂ deposition. On the other hand, the observed large initial trapping suggests that the non-controlled SiO_x interfacial region is more defective than a controlled one.