Etch of nano-TSV with smooth sidewall and excellent selection ratio for backside power delivery network

Abstract

Backside Power Delivery Network (BSPDN) is a crucial technology for integrated circuits at sub-3 nm technology nodes. The primary challenge resides in utilizing nano through silicon via (nano-TSV) to establish connections between the backside power network and buried power rails, thereby facilitating transistor powering. The key technology is to ensure a smooth sidewall morphology and prevent damage to buried power rails (BPR) due to over-etching. In this study, non-Bosch and Bosch techniques are compared using simulation. The results demonstrate that while the non-Bosch technique yields smooth sidewalls, it inevitably leads to over-etching, whereas Bosch effectively avoids over-etching. The etching of scallop-free nano-TSV is achieved by optimizing the Bosch process, which involves the use of inductively coupled plasma (ICP). Finally, metal filling of nano-TSV is successfully achieved. Thus, the nano-TSV etching method is established as viable for BSPDN.