3D PCM 中的阈下读取操作:1S1R 器件建模和存储器阵列分析

IF 2.6 4区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC
Qiuyao Yu , Guangming Zhang , Yu Lei , Xinyu Yang , Houpeng Chen , Qian Wang , Zhitang Song
{"title":"3D PCM 中的阈下读取操作:1S1R 器件建模和存储器阵列分析","authors":"Qiuyao Yu ,&nbsp;Guangming Zhang ,&nbsp;Yu Lei ,&nbsp;Xinyu Yang ,&nbsp;Houpeng Chen ,&nbsp;Qian Wang ,&nbsp;Zhitang Song","doi":"10.1016/j.mee.2024.112211","DOIUrl":null,"url":null,"abstract":"<div><p>3-D phase change memory (PCM) is one of the most promising next-generation nonvolatile memory, and the subthreshold sensing strategy can effectively improve its limited endurance. In this study, we propose a one-selector-one-resistor (1S1R) model with Monte Carlo (MC) function and provide array configurations for the worst case and the maximum bit line voltage (<em>V</em><sub><em>BL-max</em></sub>), respectively. Based on these, the read window margin (RWM) is evaluated with various array sizes, OTS threshold voltage variations (<span><math><msub><mi>σ</mi><mi>var</mi></msub></math></span>), and bias voltages (<em>V</em><sub><em>Bias</em></sub>). Our results reveal that the RWM increases as the <em>V</em><sub><em>BL</em></sub> approaches the <em>V</em><sub><em>BL-</em>max</sub>. Larger arrays lead to an increased leakage current difference, while larger <span><math><msub><mi>σ</mi><mi>var</mi></msub></math></span> values result in decreased cell current difference and <em>V</em><sub><em>BL-</em>max</sub>. The decrease in <em>V</em><sub><em>BL-max</em></sub> further deteriorates the RWM. Additionally, we analyze the optimal <em>V</em><sub><em>Bias</em></sub> for 2-deck arrays achieves a 7% reduction in leakage energy consumption and a 22.6% increase in RWM compared to the V/2 bias. The optimal <em>V</em><sub><em>Bias</em></sub> depends on OTS devices and array sizes.</p></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":null,"pages":null},"PeriodicalIF":2.6000,"publicationDate":"2024-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Subthreshold read operations in 3D PCM: 1S1R device modeling and memory array analysis\",\"authors\":\"Qiuyao Yu ,&nbsp;Guangming Zhang ,&nbsp;Yu Lei ,&nbsp;Xinyu Yang ,&nbsp;Houpeng Chen ,&nbsp;Qian Wang ,&nbsp;Zhitang Song\",\"doi\":\"10.1016/j.mee.2024.112211\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><p>3-D phase change memory (PCM) is one of the most promising next-generation nonvolatile memory, and the subthreshold sensing strategy can effectively improve its limited endurance. In this study, we propose a one-selector-one-resistor (1S1R) model with Monte Carlo (MC) function and provide array configurations for the worst case and the maximum bit line voltage (<em>V</em><sub><em>BL-max</em></sub>), respectively. Based on these, the read window margin (RWM) is evaluated with various array sizes, OTS threshold voltage variations (<span><math><msub><mi>σ</mi><mi>var</mi></msub></math></span>), and bias voltages (<em>V</em><sub><em>Bias</em></sub>). Our results reveal that the RWM increases as the <em>V</em><sub><em>BL</em></sub> approaches the <em>V</em><sub><em>BL-</em>max</sub>. Larger arrays lead to an increased leakage current difference, while larger <span><math><msub><mi>σ</mi><mi>var</mi></msub></math></span> values result in decreased cell current difference and <em>V</em><sub><em>BL-</em>max</sub>. The decrease in <em>V</em><sub><em>BL-max</em></sub> further deteriorates the RWM. Additionally, we analyze the optimal <em>V</em><sub><em>Bias</em></sub> for 2-deck arrays achieves a 7% reduction in leakage energy consumption and a 22.6% increase in RWM compared to the V/2 bias. The optimal <em>V</em><sub><em>Bias</em></sub> depends on OTS devices and array sizes.</p></div>\",\"PeriodicalId\":18557,\"journal\":{\"name\":\"Microelectronic Engineering\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":2.6000,\"publicationDate\":\"2024-07-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Microelectronic Engineering\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://www.sciencedirect.com/science/article/pii/S0167931724000807\",\"RegionNum\":4,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q2\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Microelectronic Engineering","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S0167931724000807","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0

摘要

三维相变存储器(PCM)是最有前途的下一代非易失性存储器之一,而亚阈值传感策略能有效改善其有限的耐用性。在本研究中,我们提出了一个具有蒙特卡罗(MC)函数的单选择器单电阻器(1S1R)模型,并分别提供了最坏情况和最大位线电压(VBL-max)的阵列配置。在此基础上,利用各种阵列尺寸、OTS 阈值电压变化(σvar)和偏置电压(VBias)对读取窗口余量(RWM)进行了评估。结果表明,当 VBL 接近最大 VBL 时,RWM 会增加。较大的阵列会导致漏电流差增大,而较大的 σvar 值会导致电池电流差和 VBL 最大值减小。VBL-max 的减小进一步恶化了 RWM。此外,我们还分析了双层阵列的最佳 VBias,与 V/2 偏置相比,泄漏能耗降低了 7%,RWM 提高了 22.6%。最佳 VBias 取决于 OTS 器件和阵列尺寸。
本文章由计算机程序翻译,如有差异,请以英文原文为准。

Subthreshold read operations in 3D PCM: 1S1R device modeling and memory array analysis

Subthreshold read operations in 3D PCM: 1S1R device modeling and memory array analysis

3-D phase change memory (PCM) is one of the most promising next-generation nonvolatile memory, and the subthreshold sensing strategy can effectively improve its limited endurance. In this study, we propose a one-selector-one-resistor (1S1R) model with Monte Carlo (MC) function and provide array configurations for the worst case and the maximum bit line voltage (VBL-max), respectively. Based on these, the read window margin (RWM) is evaluated with various array sizes, OTS threshold voltage variations (σvar), and bias voltages (VBias). Our results reveal that the RWM increases as the VBL approaches the VBL-max. Larger arrays lead to an increased leakage current difference, while larger σvar values result in decreased cell current difference and VBL-max. The decrease in VBL-max further deteriorates the RWM. Additionally, we analyze the optimal VBias for 2-deck arrays achieves a 7% reduction in leakage energy consumption and a 22.6% increase in RWM compared to the V/2 bias. The optimal VBias depends on OTS devices and array sizes.

求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
Microelectronic Engineering
Microelectronic Engineering 工程技术-工程:电子与电气
CiteScore
5.30
自引率
4.30%
发文量
131
审稿时长
29 days
期刊介绍: Microelectronic Engineering is the premier nanoprocessing, and nanotechnology journal focusing on fabrication of electronic, photonic, bioelectronic, electromechanic and fluidic devices and systems, and their applications in the broad areas of electronics, photonics, energy, life sciences, and environment. It covers also the expanding interdisciplinary field of "more than Moore" and "beyond Moore" integrated nanoelectronics / photonics and micro-/nano-/bio-systems. Through its unique mixture of peer-reviewed articles, reviews, accelerated publications, short and Technical notes, and the latest research news on key developments, Microelectronic Engineering provides comprehensive coverage of this exciting, interdisciplinary and dynamic new field for researchers in academia and professionals in industry.
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信