Microelectronic Engineering最新文献_第6页

Flexible fabrication of aligned multi-nanowire circuits for on-chip prototyping 用于片上原型设计的排列多纳米线电路的柔性制造

IF 2.6 4区工程技术

Microelectronic Engineering Pub Date : 2025-11-15 Epub Date: 2025-05-24 DOI: 10.1016/j.mee.2025.112363

Vidar Flodgren , Abhijit Das , Joachim E. Sestoft , Nathanael Löfström , David Alcer , Hossein Jeddi , Magnus T. Borgström , Håkan Pettersson , Jesper Nygård , Anders Mikkelsen

{"title":"Flexible fabrication of aligned multi-nanowire circuits for on-chip prototyping","authors":"Vidar Flodgren , Abhijit Das , Joachim E. Sestoft , Nathanael Löfström , David Alcer , Hossein Jeddi , Magnus T. Borgström , Håkan Pettersson , Jesper Nygård , Anders Mikkelsen","doi":"10.1016/j.mee.2025.112363","DOIUrl":"10.1016/j.mee.2025.112363","url":null,"abstract":"<div><div>Circuits of multiple deterministically positioned semiconductor nanowires (NWs) is the basis of many devices for photonic, quantum, or conventional transistor applications. To explore and iterate on the design of larger circuits, the means to quickly place and electrically evaluate NWs at target locations must be developed. We propose and demonstrate a multi-NW circuit building concept on SiO<sub>2</sub>/Si substrates, which enables us to quickly position and orient NW components into pre-designed configurations. Micro-manipulator probes are used to guide the NWs into reactive ion etched trenches, with desired designs, before contact metallization. The positioning works over a wide combination of trench widths and depths. Positioning accuracies are contingent on EBL patterning, precise up to ±10 nm. To demonstrate the concept, we create circuits of InP and InAs NWs with a wide variety of specific orientations. The concept was used to iterate a procedure for creating optimal contacts for InP NW photodiodes. Subsequently, we could fabricate and electrically probe 54 fully operational nano-photodiodes placed on three different samples, from which considerable statistics of diode performance could be obtained. Fabrication steps are directly compatible with conventional Si CMOS architecture and should function for a wide range of NW types. The accuracy and rate of placement combined with high fabrication yields enables proof-of-concept prototyping of complex circuits.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"300 ","pages":"Article 112363"},"PeriodicalIF":2.6,"publicationDate":"2025-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144205248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Field-free magnetization switching in SOT-MRAM devices with noncollinear antiferromagnets 非共线反铁磁体SOT-MRAM器件的无场磁化开关

IF 2.6 4区工程技术

Microelectronic Engineering Pub Date : 2025-11-15 Epub Date: 2025-06-08 DOI: 10.1016/j.mee.2025.112372

Bernhard Pruckner , Nils Petter Jørstad , Wolfgang Goes , Siegfried Selberherr , Viktor Sverdlov

{"title":"Field-free magnetization switching in SOT-MRAM devices with noncollinear antiferromagnets","authors":"Bernhard Pruckner , Nils Petter Jørstad , Wolfgang Goes , Siegfried Selberherr , Viktor Sverdlov","doi":"10.1016/j.mee.2025.112372","DOIUrl":"10.1016/j.mee.2025.112372","url":null,"abstract":"<div><div>Spin-orbit torque magnetoresistive random access memory (SOT-MRAM) is a promising nonvolatile memory technology that offers fast writing speed, low power, and long endurance. However, achieving deterministic perpendicular magnetization switching typically requires an external field, limiting scalability. This work explores the incorporation of noncollinear antiferromagnetic (nc-AFMs), exhibiting the magnetic spin Hall effect (MSHE), and exchange bias to enable field-free deterministic switching. MSHE has been observed in Mn<span><math><msub><mrow></mrow><mn>3</mn></msub></math></span>Sn, MnPd<span><math><msub><mrow></mrow><mn>3</mn></msub></math></span>. The ratio of out-of-plane to in-plane polarized spin-currents is crucial for field-free MSHE-driven magnetization switching. It was found that a minimum ratio is needed to drive field-free perpendicular switching. Exchange bias acting at the interface between in-plane AFM and out-of-plane ferromagnet (FM) has been demonstrated to enable field-free SOT-driven magnetization switching. We show, that exchange bias can facilitate field-free perpendicular switching in cases of a missing or too small out-of-plane polarized spin current component. We present a fully three-dimensional finite element model that couples spin currents and magnetization dynamics to simulate SOT-MRAM devices utilizing the MSHE. We show that the use of nc-AFMs eliminates the need for external fields without compromising performance, simplifying design, and boosting scalability.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"300 ","pages":"Article 112372"},"PeriodicalIF":2.6,"publicationDate":"2025-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144263517","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A laboratory system for X-ray assisted device alteration (XADA) x射线辅助设备改造（XADA）实验室系统

IF 2.6 4区工程技术

Microelectronic Engineering Pub Date : 2025-11-15 Epub Date: 2025-06-13 DOI: 10.1016/j.mee.2025.112375

S.H. Lau , W. Lo , B. Stripe , F. Su , S. Lewis , R.I. Spink , W. Yun

{"title":"A laboratory system for X-ray assisted device alteration (XADA)","authors":"S.H. Lau , W. Lo , B. Stripe , F. Su , S. Lewis , R.I. Spink , W. Yun","doi":"10.1016/j.mee.2025.112375","DOIUrl":"10.1016/j.mee.2025.112375","url":null,"abstract":"<div><div>The shift toward backside power delivery (BPD) architecture and 3D stacking of integrated circuits (ICs) introduces significant challenges for failure analysis (FA). Traditional near-infrared (NIR)-based fault isolation techniques such as Laser-Assisted Device Alteration (LADA) are rendered ineffective by NIR-blocking metallization layers. X-ray-Assisted Device Alteration (XADA) emerges as a powerful alternative, leveraging the penetrating capability of x-rays to target and alter transistor behavior. The ability of x-rays to penetrate near-infrared opaque materials is heavily exploited for non-destructive inspection of packaged parts and circuit boards. For these applications, the ability of the ionizing x-rays to alter transistor characteristics is undesirable. Recently, however, the intentional exploitation of these ionizing effects for targeted device alteration using a micro-focused, scanning x-ray beam, analogous to LADA, has been explored. This paper provides an expanded analysis of XADA, introducing advancements in x-ray source design, focusing optics, and experimental methodologies. Additionally, system-level innovations, including high-precision navigation and co-axial optical setups, position XADA as a transformative tool for FA of BPD-era ICs.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"300 ","pages":"Article 112375"},"PeriodicalIF":2.6,"publicationDate":"2025-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144322487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Actinic defect inspection and characterization for extreme ultraviolet mask blanks 极紫外掩模毛坯的光化缺陷检测与表征

IF 2.6 4区工程技术

Microelectronic Engineering Pub Date : 2025-11-15 Epub Date: 2025-07-10 DOI: 10.1016/j.mee.2025.112378

Hala Mohammad , Bochao Li , Jamilu Tijjani Baraya , Zhenlong Zhao , Xiaowei Song , Jingquan Lin

引用次数: 0

Performance enhancement of a spacer-engineered GS SOI n-FinFET with 10 nm gate length 栅极长度为10nm的间隔设计的GS SOI n-FinFET的性能增强

IF 2.6 4区工程技术

Microelectronic Engineering Pub Date : 2025-11-15 Epub Date: 2025-07-16 DOI: 10.1016/j.mee.2025.112383

Bhavya Kumar , Anurag Somayajula , Vishnu Sajith , Tanish Aggarwal , Rishu Chaujar

{"title":"Performance enhancement of a spacer-engineered GS SOI n-FinFET with 10 nm gate length","authors":"Bhavya Kumar , Anurag Somayajula , Vishnu Sajith , Tanish Aggarwal , Rishu Chaujar","doi":"10.1016/j.mee.2025.112383","DOIUrl":"10.1016/j.mee.2025.112383","url":null,"abstract":"<div><div>This study showcases the improvement in conventional SOI n-FinFET devices with the incorporation of a high-K spacer and gate stack (GS) engineering at 10 nm gate length. Three FinFET configurations were considered for comparison, and the simulated results show significant improvements in the analog and RF performance of the proposed configuration. Analog parameters such as the I<sub>ON</sub>/I<sub>OFF</sub> ratio increased almost 10<sup>4</sup> times, subthreshold swing reduced by ∼60 %; transconductance increased by ∼92 %, QF improved by ∼382 %, TGF enhanced by ∼302 %, intrinsic gain increased by almost 8 times, and early voltage by almost 5 times, indicating the proposed device is suitable for high-performance CMOS circuits. Further, the RF analysis is performed with parameters like cut-off frequency, GFP, TFP, etc., exhibiting considerable improvement for the proposed configuration. Thus, gate stacking and spacer engineering significantly improve the FinFET performance, enhancing the analog and RF capabilities of semiconductor devices for more efficient integrated circuits.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"300 ","pages":"Article 112383"},"PeriodicalIF":2.6,"publicationDate":"2025-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144653875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Use of a hybrid metrology approach to develop holistic filtration solutions in hydrogen peroxide 使用混合计量方法开发过氧化氢整体过滤解决方案

IF 2.6 4区工程技术

Microelectronic Engineering Pub Date : 2025-11-15 Epub Date: 2025-07-12 DOI: 10.1016/j.mee.2025.112381

Kusum Maharjan , Nicole Williams , Sally Huang , Siddarth Sampath , Briana Dufek , Suhas Ketkar , Austin Schultz

{"title":"Use of a hybrid metrology approach to develop holistic filtration solutions in hydrogen peroxide","authors":"Kusum Maharjan , Nicole Williams , Sally Huang , Siddarth Sampath , Briana Dufek , Suhas Ketkar , Austin Schultz","doi":"10.1016/j.mee.2025.112381","DOIUrl":"10.1016/j.mee.2025.112381","url":null,"abstract":"<div><div>All semiconductor manufacturers are driving to advance their process efficiency and effectiveness to deliver improved performance. To achieve such improvements with each generation of new semiconductor devices while maintaining high reliability and yield, strict contamination control must be established for process chemicals and gases. Contaminants in these materials can be present in various forms, such as organics, gels, solid particles, anions, cations, polymers, etc., and are typically controlled using membrane-based filtration. To ensure that the appropriate filtration solutions are implemented, a two-step process is required. First, one must identify/characterize the contaminants present in the semiconductor grade chemistry using multiple analytical techniques to develop a diverse profile of contaminants and then use that knowledge to optimize filtration schemes across the supply chain to ensure end-to-end impurity control. In this paper, a hybrid metrology approach was utilized to first understand the contamination profile of semiconductor grade hydrogen peroxide (H<sub>2</sub>O<sub>2</sub>) at 30 % concentration then evaluate the effectiveness of different filter membranes in removing these contaminants from the chemical.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"300 ","pages":"Article 112381"},"PeriodicalIF":2.6,"publicationDate":"2025-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144604603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Potential of ultrahigh-vacuum based surface treatments in silicon technology 超高真空基表面处理在硅技术中的潜力

IF 2.6 4区工程技术

Microelectronic Engineering Pub Date : 2025-11-15 Epub Date: 2025-07-19 DOI: 10.1016/j.mee.2025.112382

Z. Jahanshah Rad, M. Miettinen, R. Punkkinen, P. Suomalainen, M. Punkkinen, P. Laukkanen, K. Kokko

{"title":"Potential of ultrahigh-vacuum based surface treatments in silicon technology","authors":"Z. Jahanshah Rad, M. Miettinen, R. Punkkinen, P. Suomalainen, M. Punkkinen, P. Laukkanen, K. Kokko","doi":"10.1016/j.mee.2025.112382","DOIUrl":"10.1016/j.mee.2025.112382","url":null,"abstract":"<div><div>Ultrahigh vacuum (UHV) environment with the background pressure in the range of 1‧10<sup>−15</sup>–1‧10<sup>−11</sup> bar is common in surface-science experiments, but UHV-based material treatments are rarely used in the current silicon technology. UHV methods might however provide a clear benefit to the technology when atomic-level cleanliness and crystalline order of Si surfaces (interfaces) as well as dry-cleaning methods for the surfaces become relevant to the development of Si devices. We have studied effects of some UHV-based treatments on the properties of Si surfaces and of thin oxide films on Si. Exposing Si, pre-cleaned by the RCA recipe with the final HF dip, to mere hydrogen (H<sub>2</sub>) gas in UHV chamber at the Si temperature of 200 °C increases a crystalline degree of the Si surface according to low-energy electron diffraction. Effects of postheating in UHV are also studied for different oxidized Si surfaces. Wet chemically oxidized (RCA without HF dip) Si was heated step-by-step up to 800 °C in UHV until the oxide removal is strongly enhanced. Both crystalline degree of the RCA chemical oxide and surface roughness increase with the UHV post-heating at 500–800 °C. Exposing native-oxide covered sidewalls of Si diodes to mere oxygen (O<sub>2</sub>) gas in UHV chamber at Si temperature of 350 °C (i) increases amount of SiO<sub>2</sub> at the sidewalls according to x-ray photoelectron spectroscopy, (ii) decreases amount of the band-gap electron levels at the sidewalls according to scanning tunneling spectroscopy, and (iii) provides a durable decrease in the diode leakage current.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"300 ","pages":"Article 112382"},"PeriodicalIF":2.6,"publicationDate":"2025-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144663052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Research on stress mutation of fiber optic gyroscope 光纤陀螺仪应力突变研究

IF 2.6 4区工程技术

Microelectronic Engineering Pub Date : 2025-11-15 Epub Date: 2025-05-29 DOI: 10.1016/j.mee.2025.112362

Daixuan Wu , Boshang Lu , Zhiyuan Xu , Qian Li , Jian Wang , Wei Xun , Hu Zhao

{"title":"Research on stress mutation of fiber optic gyroscope","authors":"Daixuan Wu , Boshang Lu , Zhiyuan Xu , Qian Li , Jian Wang , Wei Xun , Hu Zhao","doi":"10.1016/j.mee.2025.112362","DOIUrl":"10.1016/j.mee.2025.112362","url":null,"abstract":"<div><div>Temperature-variation sensitivity of fiber-optic rings is a bottleneck problem that restricts the engineering application of fiber optic gyroscopes in high-precision fields. At present, techniques such as quadrupole-symmetry and octupole-symmetry schemes are commonly used to enhance the length and position symmetry of fiber optic rings, achieving mutual cancellation of external temperature changes. This article is based on engineering applications, focusing on the conventional symmetry of fiber optic rings, and focusing on the process factors that affect the stress symmetry of fiber optic rings. It is found that there is a significant stress mutation in the bottom layer of the fiber optic ring using the conventional four pole and eight pole symmetric winding schemes. By analyzing the curing mechanism and the stress curve before and after curing, it is found that the tension of the fiber optic ring is affected. The difference in modulus between the fiber optic and the skeleton jointly causes a sudden change in the underlying stress curve. This paper proposes a buffer layer design method with batch-producible process, which can effectively suppress stress mutations in the central area of the fiber optic ring. The gyroscope products equipped with this process fiber optic ring can improve the temperature and bias instability index by 29 % while ensuring vibration performance. It has successfully achieved batch production of 0.01°/h fiber-optic gyroscopes, completed the production and development of over 3000 axes, and demonstrated significant engineering application value</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"300 ","pages":"Article 112362"},"PeriodicalIF":2.6,"publicationDate":"2025-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144290509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Unsupervised domain adaptation for IC image segmentation with structural constraint and pseudo supervision 基于结构约束和伪监督的无监督域自适应集成电路图像分割

IF 2.6 4区工程技术

Microelectronic Engineering Pub Date : 2025-11-15 Epub Date: 2025-06-06 DOI: 10.1016/j.mee.2025.112373

Deruo Cheng, Yee-Yang Tee, Xuenong Hong, Tong Lin, Yiqiong Shi, Bah-Hwee Gwee

{"title":"Unsupervised domain adaptation for IC image segmentation with structural constraint and pseudo supervision","authors":"Deruo Cheng, Yee-Yang Tee, Xuenong Hong, Tong Lin, Yiqiong Shi, Bah-Hwee Gwee","doi":"10.1016/j.mee.2025.112373","DOIUrl":"10.1016/j.mee.2025.112373","url":null,"abstract":"<div><div>Integrated circuit (IC) image segmentation is crucial for functional verification and trustworthiness evaluation of ICs manufactured in the globalized supply chain. Conventional supervised deep learning models for IC image segmentation face significant challenges of domain shift when applied across IC layers. To address this, we propose a domain adaptation framework with Structural Constraint and Pseudo Supervision (SCPS) for improving segmentation performance on target datasets collected from different IC layers. Our proposed SCPS first leverages CycleGAN to synthesize target dataset with input masks from source dataset, where a constraint is imposed onto the structural patterns of circuit elements in synthetic target images and source masks to improve their structural consistency. It further utilizes unlabeled real target images through domain mixing and image−/feature-level augmentation with pseudo supervision during training. With experiments on target datasets collected from two different IC chip layers, our proposed SCPS outperforms existing methods in the accuracy of circuit connections retrieved from IC image segmentation, while maintaining comparable performance in terms of commonly used segmentation metrics.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"300 ","pages":"Article 112373"},"PeriodicalIF":2.6,"publicationDate":"2025-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144263516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Variability analysis in memristors based on electrodeposited prussian blue 基于电沉积普鲁士蓝的忆阻器变异性分析

IF 2.6 4区工程技术

Microelectronic Engineering Pub Date : 2025-11-15 Epub Date: 2025-06-19 DOI: 10.1016/j.mee.2025.112376

L.B. Avila , A. Cantudo , M.A. Villena , D. Maldonado , F. Abreu Araujo , C.K. Müller , J.B. Roldán

{"title":"Variability analysis in memristors based on electrodeposited prussian blue","authors":"L.B. Avila , A. Cantudo , M.A. Villena , D. Maldonado , F. Abreu Araujo , C.K. Müller , J.B. Roldán","doi":"10.1016/j.mee.2025.112376","DOIUrl":"10.1016/j.mee.2025.112376","url":null,"abstract":"<div><div>This work presents a comprehensive analysis of the variability and reliability of the resistive switching (RS) behavior in Prussian Blue (a mixed-valence iron(III/II) hexacyanoferrate compound) thin films, used as the active layer. These films are fabricated through a simple and scalable electrochemical process, and exhibit robust bipolar resistive switching, making them suitable both for neuromorphic computing applications and hardware cryptography. A detailed statistical evaluation was conducted over 100 consecutive switching cycles using multiple parameter extraction techniques to assess cycle-to-cycle (C2C) variability in key RS parameters, including set/reset voltages and corresponding currents. One and two-dimensional coefficients of variation (1DCV and 2DCV) were calculated to quantify variability and identify application potential. Results demonstrate moderate variability compatible with neuromorphic computing and cryptographic functionalities, including physical unclonable functions and true random number generation. These findings position Prussian Blue-based memristors as promising candidates for low-cost, stable, and multifunctional memory.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"300 ","pages":"Article 112376"},"PeriodicalIF":2.6,"publicationDate":"2025-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144510669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0