Microelectronic Engineering最新文献_第5页

Improved positive bias temperature instability of n-type vertical C-shaped-channel nanosheet FET by forming gas annealing 形成气体退火改善n型垂直c形通道纳米片场效应管的正偏置温度不稳定性

IF 2.6 4区工程技术

Microelectronic Engineering Pub Date : 2025-05-16 DOI: 10.1016/j.mee.2025.112357

Yunfei Shi , Songyi Jiang , Hong Yang , Yongkui Zhang , Longda Zhou , Zhigang Ji , Qianqian Liu , Qi Wang , Huilong Zhu , Jun Luo , Wenwu Wang

引用次数: 0

Recent advancement in β-Ga2O3 MOSFETs: From material growth to device architectures for high-power electronics β-Ga2O3 mosfet的最新进展：从材料生长到大功率电子器件架构

IF 2.6 4区工程技术

Microelectronic Engineering Pub Date : 2025-05-14 DOI: 10.1016/j.mee.2025.112359

P. Murugapandiyan , A.S. Augustine Fletcher , Md. Tanvir Hasan , N. Ramkumar , A. Revathy

{"title":"Recent advancement in β-Ga2O3 MOSFETs: From material growth to device architectures for high-power electronics","authors":"P. Murugapandiyan , A.S. Augustine Fletcher , Md. Tanvir Hasan , N. Ramkumar , A. Revathy","doi":"10.1016/j.mee.2025.112359","DOIUrl":"10.1016/j.mee.2025.112359","url":null,"abstract":"<div><div>Beta‑gallium oxide (β-Ga<sub>2</sub>O<sub>3</sub>) has emerged as a promising semiconductor material for next-generation power electronics due to its ultra-wide bandgap (4.9 eV), exceptional breakdown electric field (8 MV/cm), and compatibility with cost-effective melt growth methods for producing large-area single crystals. This comprehensive review examines recent advances in β-Ga<sub>2</sub>O<sub>3</sub> metal-oxide-semiconductor field-effect transistors (MOSFETs), spanning from material synthesis to device implementation. The review then investigates device architectures, examining both depletion-mode and enhancement-mode β-Ga<sub>2</sub>O<sub>3</sub> MOSFETs. We highlight crucial design elements including field plates, innovative gate structures, and channel engineering techniques that have enabled devices with breakdown voltages exceeding 2.3 kV and power figures of merit surpassing 150 MW/cm<sup>2</sup>. Additionally, we address significant challenges, particularly thermal management issues stemming from β-Ga<sub>2</sub>O<sub>3</sub>'s relatively low thermal conductivity (10–20 W/m·K) and the current absence of p-type doping capability, discussing various proposed solutions including diamond heat spreaders, heterogeneous substrate integration, and advanced packaging approaches. Finally, we examine emerging concepts such as nanomembrane transistors, fin structures, and heterojunction FETs, concluding with insights on future research directions for this promising semiconductor technology.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"299 ","pages":"Article 112359"},"PeriodicalIF":2.6,"publicationDate":"2025-05-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144071119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Study on different failure mechanisms of MOSFET caused by different oxide defects in 14 nm FinFET IC 14nm FinFET IC中不同氧化物缺陷导致MOSFET失效机制的研究

IF 2.6 4区工程技术

Microelectronic Engineering Pub Date : 2025-05-10 DOI: 10.1016/j.mee.2025.112350

Yanfen Wang, Shijun Zheng, Shan Zhang, Junsheng Wang, Guang Lu, Gaojie Wen

{"title":"Study on different failure mechanisms of MOSFET caused by different oxide defects in 14 nm FinFET IC","authors":"Yanfen Wang, Shijun Zheng, Shan Zhang, Junsheng Wang, Guang Lu, Gaojie Wen","doi":"10.1016/j.mee.2025.112350","DOIUrl":"10.1016/j.mee.2025.112350","url":null,"abstract":"<div><div>With the advent of FinFET technology, especially in the application of 14 nm and above nodes, the front-end-of-line (FEOL) defects at the transistor level have become increasingly significant. These minute FEOL defects have a critical impact on the yield and reliability of the ultimate chipset. This paper focuses on two types of FEOL defects identified in 14 nm FinFET technology. The research shows that both of these FEOL defects can lead to leakage in MOSFETs. We have conducted an in-depth analysis of the distinct failure mechanisms of these two defects and their potential formation causes. It is expected to help wafer factories achieve effective improvements. The study indicates that these two failure modes might be triggered by oxide defects in different steps of the FEOL process flow. Specifically, in one case, dielectric breakdown-induced epitaxy (DBIE) causes NMOS gate leakage, which might be ascribed to the presence of defects in the bottom interface layer (BIL) of the oxide. In another instance, PMOS leakage caused by germanium bridge defects might result from oxide defects as the etch stop layer (ESL) and the influence of subsequent process steps on the defects. This research provides an essential guiding direction for wafer factories to optimize the manufacturing process of 14 nm FinFET products and improve yield and quality. At the same time, this study also offers a valuable reference basis for the failure analysis of FinFET devices.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"299 ","pages":"Article 112350"},"PeriodicalIF":2.6,"publicationDate":"2025-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143927984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A RRAM-based logic in memory DES implementation against power attacks 一个基于ram的逻辑内存DES实现，防止电源攻击

IF 2.6 4区工程技术

Microelectronic Engineering Pub Date : 2025-05-09 DOI: 10.1016/j.mee.2025.112356

Haoxiong Bi , Pengju Wang , Jiabao Ye , Liang Zhao , Yuejun Zhang , Bing Chen

引用次数: 0

Seed-assisted growth of large-area β'-In2Se3 ferroelectric thin films β′-In2Se3铁电薄膜的种子辅助生长

IF 2.6 4区工程技术

Microelectronic Engineering Pub Date : 2025-05-07 DOI: 10.1016/j.mee.2025.112354

Lingrui Zou , Pu Feng , Peipei Jing , Chaoqun Dang , Haiming Zhu , Xin He , Lijie Zhang , Tao Wang , Fei Xue

{"title":"Seed-assisted growth of large-area β'-In2Se3 ferroelectric thin films","authors":"Lingrui Zou , Pu Feng , Peipei Jing , Chaoqun Dang , Haiming Zhu , Xin He , Lijie Zhang , Tao Wang , Fei Xue","doi":"10.1016/j.mee.2025.112354","DOIUrl":"10.1016/j.mee.2025.112354","url":null,"abstract":"<div><div>The recent discovery of two-dimensional ferroelectric semiconductors, such as In<sub>2</sub>Se<sub>3</sub>, has opened promising avenues for ultra-thin micro-nano electronic devices, and energy-efficient neuromorphic systems. Despite these exciting prospects, achieving large-area, high-quality, layer-controlled growth of single-phase In<sub>2</sub>Se<sub>3</sub> remains a considerable challenge. In this study, we present a seed-assisted strategy for growing uniform, centimeter-scale β'-In<sub>2</sub>Se<sub>3</sub> thin films by mixing In<sub>2</sub>O<sub>3</sub> and In<sub>2</sub>Se<sub>3</sub> single crystals in a specific ratio. The resulting β'-In<sub>2</sub>Se<sub>3</sub> phase and composition are verified through X-ray diffraction, transmission electron microscopy, and Raman spectroscopy. Furthermore, the ferroelectric properties and domain configurations have been characterized by using polarized light microscopy and piezoresponse force microscopy. Importantly, we investigate the topological evolution of ferroelectric domains across films with varying thicknesses, revealing insights into domain structure modulation. This growth method not only provides a scalable route for synthesizing similar ferroelectric two-dimensional materials but also a possibility for the practical integration of β'-In<sub>2</sub>Se<sub>3</sub> in optoelectronic, neuromorphic, and other advanced micro-nano electronic applications.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"299 ","pages":"Article 112354"},"PeriodicalIF":2.6,"publicationDate":"2025-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143918161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Finite element modeling analysis of misalignment impact on simulated electrical RC in scaling hybrid bonding pairs 不对准对缩放杂化键对模拟电RC影响的有限元建模分析

IF 2.6 4区工程技术

Microelectronic Engineering Pub Date : 2025-05-05 DOI: 10.1016/j.mee.2025.112347

Guoqiang Zhao , Yi Zhao

引用次数: 0

A new tunable floating memristor emulator circuit with long-term memory 一种具有长期记忆的可调浮动忆阻器仿真电路

IF 2.6 4区工程技术

Microelectronic Engineering Pub Date : 2025-05-02 DOI: 10.1016/j.mee.2025.112355

Jiaheng Pan , Yanwei Sun , Shengyao Jia , Xudong Shen , Yiran Wang , Shien Wu , Cheng Pan , Mang Shi , Ge Shi

{"title":"A new tunable floating memristor emulator circuit with long-term memory","authors":"Jiaheng Pan , Yanwei Sun , Shengyao Jia , Xudong Shen , Yiran Wang , Shien Wu , Cheng Pan , Mang Shi , Ge Shi","doi":"10.1016/j.mee.2025.112355","DOIUrl":"10.1016/j.mee.2025.112355","url":null,"abstract":"<div><div>In this research article, we propose a tunable floating-type memristor emulator circuit with long-term memory (LTM) capabilities. The overall circuit consists of a Voltage Differential Transconductance Amplifier (VDTA), a Voltage Differential Complementary Amplifier (VDCA), and other basic components. The proposed emulator effectively prevents charge leakage on the capacitor by incorporating a switching circuit, thereby achieving long-term memory functionality. The emulator operates stably at a frequency of 10 MHz and supports seamless switching between incremental and decremental modes by altering the polarity of the input voltage. Moreover, the emulator exhibits excellent tunability, allowing adjustments to the equivalent memristor model by modifying the bias voltage and the aspect ratio of MOS transistors. The proposed emulator has been laid out and simulated using TSMC 0.18 μm process parameters in the Cadence Virtuoso platform. The simulation results align perfectly with the design and analysis, confirming the feasibility of the circuit. Finally, we explore potential applications of the proposed emulator in read-write circuit and memristor array circuit.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"299 ","pages":"Article 112355"},"PeriodicalIF":2.6,"publicationDate":"2025-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143911628","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Strategies and approaches for RFID tag integration in textiles 纺织品中RFID标签集成的策略与方法

IF 2.6 4区工程技术

Microelectronic Engineering Pub Date : 2025-05-02 DOI: 10.1016/j.mee.2025.112358

J. Joslin Percy , S. Kanthamani , S. Mohamed Mansoor Roomi , Thennarasan Sabapathy

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The role of etching gas purity in C4F8/Ar plasma to optimize SiO2 etching process C4F8/Ar等离子体中蚀刻气体纯度对SiO2蚀刻工艺优化的作用

IF 2.6 4区工程技术

Microelectronic Engineering Pub Date : 2025-05-02 DOI: 10.1016/j.mee.2025.112353

Anhan Liu , Shijun Yu , Shingo Nakamura , Akinari Sugiyama , Takashi Nishikawa , Dongwei Xu , Xiao Jin , Daixuan Wu , He Tian

{"title":"The role of etching gas purity in C4F8/Ar plasma to optimize SiO2 etching process","authors":"Anhan Liu , Shijun Yu , Shingo Nakamura , Akinari Sugiyama , Takashi Nishikawa , Dongwei Xu , Xiao Jin , Daixuan Wu , He Tian","doi":"10.1016/j.mee.2025.112353","DOIUrl":"10.1016/j.mee.2025.112353","url":null,"abstract":"<div><div>The relentless miniaturization of critical feature sizes in integrated circuits has set increasingly stringent demands on the precision of via etching processes. Current research predominantly focuses on the development of gases and optimization of processes. However, the role of etching gas purity and the impact of gas impurities have not yet been the subject of dedicated studies. Here, the etching behavior of silicon dioxide using two different purities of etching gases is investigated, examining the etching rate and morphology of SiO<sub>2</sub> films under identical etching parameters. Compared to 99.999 % purity, the 99.99999 % purity C<sub>4</sub>F<sub>8</sub> gas achieves a more stable and uniform etching rate with sidewall angles of 86.6° (closer to a 90° angle). This is primarily attributed to the reduction of etch-active impurities in the C<sub>4</sub>F<sub>8</sub> gas, which decreases etching variability and minimizes damage to the sidewall fluorocarbon protective layer. Our research provides theoretical and experimental support for the advancement of subsequent etching simulation studies and the application of high-purity etching gases.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"299 ","pages":"Article 112353"},"PeriodicalIF":2.6,"publicationDate":"2025-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143899199","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

TCAD simulations of radiation damage in 4H-SiC 4H-SiC辐射损伤的TCAD模拟

IF 2.6 4区工程技术

Microelectronic Engineering Pub Date : 2025-05-02 DOI: 10.1016/j.mee.2025.112352

Jürgen Burin, Christopher Hahn, Philipp Gaggl, Andreas Gsponer, Simon Waid, Thomas Bergauer

引用次数: 0