14nm FinFET IC中不同氧化物缺陷导致MOSFET失效机制的研究

IF 3.1 4区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC
Yanfen Wang, Shijun Zheng, Shan Zhang, Junsheng Wang, Guang Lu, Gaojie Wen
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引用次数: 0

摘要

随着FinFET技术的出现,特别是在14nm及以上节点的应用中,晶体管级的前端线(FEOL)缺陷变得越来越明显。这些微小的FEOL缺陷对最终芯片组的良率和可靠性具有关键影响。本文重点研究了在14nm FinFET技术中发现的两类FEOL缺陷。研究表明,这两种FEOL缺陷都会导致mosfet的泄漏。我们对这两种缺陷的不同失效机制及其可能的形成原因进行了深入分析。它有望帮助晶圆厂实现有效的改进。研究表明,这两种失效模式可能是由FEOL工艺流程不同步骤的氧化缺陷引发的。具体来说,在一种情况下,介质击穿诱导外延(DBIE)导致NMOS栅极泄漏,这可能归因于氧化物底部界面层(BIL)中存在缺陷。在另一种情况下,锗桥缺陷引起的PMOS泄漏可能是由于作为蚀刻停止层(ESL)的氧化物缺陷以及后续工艺步骤对缺陷的影响。该研究为晶圆厂优化14nm FinFET产品的制造工艺,提高良率和质量提供了重要的指导方向。同时,本研究也为FinFET器件的失效分析提供了有价值的参考依据。
本文章由计算机程序翻译,如有差异,请以英文原文为准。

Study on different failure mechanisms of MOSFET caused by different oxide defects in 14 nm FinFET IC

Study on different failure mechanisms of MOSFET caused by different oxide defects in 14 nm FinFET IC
With the advent of FinFET technology, especially in the application of 14 nm and above nodes, the front-end-of-line (FEOL) defects at the transistor level have become increasingly significant. These minute FEOL defects have a critical impact on the yield and reliability of the ultimate chipset. This paper focuses on two types of FEOL defects identified in 14 nm FinFET technology. The research shows that both of these FEOL defects can lead to leakage in MOSFETs. We have conducted an in-depth analysis of the distinct failure mechanisms of these two defects and their potential formation causes. It is expected to help wafer factories achieve effective improvements. The study indicates that these two failure modes might be triggered by oxide defects in different steps of the FEOL process flow. Specifically, in one case, dielectric breakdown-induced epitaxy (DBIE) causes NMOS gate leakage, which might be ascribed to the presence of defects in the bottom interface layer (BIL) of the oxide. In another instance, PMOS leakage caused by germanium bridge defects might result from oxide defects as the etch stop layer (ESL) and the influence of subsequent process steps on the defects. This research provides an essential guiding direction for wafer factories to optimize the manufacturing process of 14 nm FinFET products and improve yield and quality. At the same time, this study also offers a valuable reference basis for the failure analysis of FinFET devices.
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来源期刊
Microelectronic Engineering
Microelectronic Engineering 工程技术-工程:电子与电气
CiteScore
5.30
自引率
4.30%
发文量
131
审稿时长
29 days
期刊介绍: Microelectronic Engineering is the premier nanoprocessing, and nanotechnology journal focusing on fabrication of electronic, photonic, bioelectronic, electromechanic and fluidic devices and systems, and their applications in the broad areas of electronics, photonics, energy, life sciences, and environment. It covers also the expanding interdisciplinary field of "more than Moore" and "beyond Moore" integrated nanoelectronics / photonics and micro-/nano-/bio-systems. Through its unique mixture of peer-reviewed articles, reviews, accelerated publications, short and Technical notes, and the latest research news on key developments, Microelectronic Engineering provides comprehensive coverage of this exciting, interdisciplinary and dynamic new field for researchers in academia and professionals in industry.
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