Proceedings of the 2004 IEEE Dallas/CAS Workshop Implementation of High Performance Circuits最新文献

A 14-bit 20-Msamples/s pipelined A/D converter with high slewing amplifier 具有高回转放大器的14位20 m采样/s的流水线A/D转换器

Proceedings of the 2004 IEEE Dallas/CAS Workshop Implementation of High Performance Circuits Pub Date : 2004-11-30 DOI: 10.1109/DCAS.2004.1360447

M. Kinyua, F. Maloberti, W. Gosney

引用次数: 3

Clocking and synchronization in sub-90 nm system-on-chip (SoC) designs sub- 90nm片上系统(SoC)设计中的时钟和同步

Proceedings of the 2004 IEEE Dallas/CAS Workshop Implementation of High Performance Circuits Pub Date : 2004-11-30 DOI: 10.1109/DCAS.2004.1360436

R. Sridhar

引用次数: 1

A gate leakage reduction strategy for sub-70 nm memory circuits 一种用于70nm以下存储电路的栅极泄漏减少策略

Proceedings of the 2004 IEEE Dallas/CAS Workshop Implementation of High Performance Circuits Pub Date : 2004-11-30 DOI: 10.1109/DCAS.2004.1360446

P. Elakkumanan, Charan Thondapu, R. Sridhar

引用次数: 29

Decap aware sleep transistor design Decap感知休眠晶体管设计

Proceedings of the 2004 IEEE Dallas/CAS Workshop Implementation of High Performance Circuits Pub Date : 2004-11-30 DOI: 10.1109/DCAS.2004.1360453

Ramaprasath Vilangudipitchai, P. Balsara

引用次数: 2

Electronic dispersion compensation for 10 Gbps data transmission over multi-mode fibers 多模光纤上10gbps数据传输的电子色散补偿

Proceedings of the 2004 IEEE Dallas/CAS Workshop Implementation of High Performance Circuits Pub Date : 2004-11-30 DOI: 10.1109/DCAS.2004.1360450

Hao Liu, Xiaofeng Lin, Youngjune Kim, Jin Liu, Sungying Jung

引用次数: 0

A 16b 65 MSps pipeline ADC core with 230 fs clock jitter in 3.3 V SiGe BiCMOS: from simulation to silicon 在3.3 V SiGe BiCMOS中，具有230 fs时钟抖动的16b 65 MSps流水线ADC核心:从模拟到硅

Proceedings of the 2004 IEEE Dallas/CAS Workshop Implementation of High Performance Circuits Pub Date : 2004-11-30 DOI: 10.1109/DCAS.2004.1360455

A. Zanchi, F. Tsay, I. Papantonopoulos

引用次数: 0

DSP-coupled 2.4 GHz RF transmitter in 130 nm CMOS dsp耦合2.4 GHz射频发射器在130纳米CMOS

Proceedings of the 2004 IEEE Dallas/CAS Workshop Implementation of High Performance Circuits Pub Date : 2004-11-30 DOI: 10.1109/DCAS.2004.1360451

R. Staszewski, R. Staszweski, J. Wallberg, T. Jung, C. Hung, D. Leipold, K. Maggio, P. Balsara

{"title":"DSP-coupled 2.4 GHz RF transmitter in 130 nm CMOS","authors":"R. Staszewski, R. Staszweski, J. Wallberg, T. Jung, C. Hung, D. Leipold, K. Maggio, P. Balsara","doi":"10.1109/DCAS.2004.1360451","DOIUrl":"https://doi.org/10.1109/DCAS.2004.1360451","url":null,"abstract":"We present an IC chip that integrates a TMS320C54x DSP. which is commonly used in cellular phones, with a multiGHz digital RF transmitter that meets the Bluetooth specifications. The RF transmitter is tightly coupled with the DSP and is directly mapped to its address space. The transmitter architecture is based on an all-digital PLL, which is built from the ground up using digital techniques and digital creation flow that exploit high speed and high density of a deep-submicron CMOS process while avoiding its weaker handling of voltage. The frequency synthesizer features a wideband frequency modulation capability. Due to its programmability, flexibility and portability, the digital RF transmitter serves as a foundation of a digital radio processor (DRP). As part of the digital flow, the digitally-controlled oscillator (DCO) and a class-E power-amplifier are created as ASIC cells with digital I/O's. All digital blocks, including the 2.4 GHz logic, are synthesized from VHDL and auto routed. The use of VHDL allows for a tight and seamless integration of RF with the DSP. To take advantage of the direct DSP-RF coupling and to demonstrate a software-defined radio (SDR) capability, a DSP program is written to perform modulation of the GSM standard. The chip is fabricated in a baseline 130 nm CMOS process with no analog extensions.","PeriodicalId":185376,"journal":{"name":"Proceedings of the 2004 IEEE Dallas/CAS Workshop Implementation of High Performance Circuits","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115208082","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Impact of selective process bias (SPB) of interconnects on circuit delay 互连选择性工艺偏置(SPB)对电路延迟的影响

Proceedings of the 2004 IEEE Dallas/CAS Workshop Implementation of High Performance Circuits Pub Date : 2004-11-30 DOI: 10.1109/DCAS.2004.1360449

M. Kulkarni, N. Nagaraj, A. Marshall, Viet Le

引用次数: 4

High-speed digital circuits for a 2.4 GHz all-digital RF frequency synthesizer in 130 nm CMOS 1.3 nm CMOS 2.4 GHz全数字射频频率合成器的高速数字电路

Proceedings of the 2004 IEEE Dallas/CAS Workshop Implementation of High Performance Circuits Pub Date : 2004-11-30 DOI: 10.1109/DCAS.2004.1360452

R. Staszewski, J. Wallberg, Jinseok Koh, P. Balsara

{"title":"High-speed digital circuits for a 2.4 GHz all-digital RF frequency synthesizer in 130 nm CMOS","authors":"R. Staszewski, J. Wallberg, Jinseok Koh, P. Balsara","doi":"10.1109/DCAS.2004.1360452","DOIUrl":"https://doi.org/10.1109/DCAS.2004.1360452","url":null,"abstract":"We present high-speed digital circuits that comprise the first ever reported all-digital 2.4 GHz frequency synthesizer and transmitter that meet the Bluetooth specifications. The chip is built in a digital 130 nm CMOS process with no analog extensions and features high logic gate density of 150 kgates per mm/sup 2/. The transmitter architecture is based on an all-digital phase-locked loop (AD-PLL), which is built from the ground up using digital techniques that exploit high speed and high density of a deep-submicron CMOS process while avoiding its weaker handling of voltage resolution. We also present a high-performance flip-flop used in this design. It features low CLK-to-Q delay and negative setup time. Because the flip-flop is symmetrical along the vertical axis, the resolution window is symmetrical for rising and falling data transitions in the time-to-digital converter (TDC). The RF transmitter area occupies only 0.54 mm/sup 2/ and the current consumption is 49 mA at 1.5 V supply and 4 mW of RF output, and includes the companion DSP. This proves attractiveness and competitiveness of the \"digital RF\" approach whose goal is to replace RF functions with high-speed digital logic gates.","PeriodicalId":185376,"journal":{"name":"Proceedings of the 2004 IEEE Dallas/CAS Workshop Implementation of High Performance Circuits","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123950291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Advanced circuit techniques for high-performance microprocessor and low-power DSPs 高性能微处理器和低功耗dsp的先进电路技术

Proceedings of the 2004 IEEE Dallas/CAS Workshop Implementation of High Performance Circuits Pub Date : 2004-11-30 DOI: 10.1109/DCAS.2004.1360432

S. Mathew, R. Krishnamurthy, M. Anders, S. Hsu, S. Borkar

引用次数: 2