High-speed digital circuits for a 2.4 GHz all-digital RF frequency synthesizer in 130 nm CMOS

Abstract

We present high-speed digital circuits that comprise the first ever reported all-digital 2.4 GHz frequency synthesizer and transmitter that meet the Bluetooth specifications. The chip is built in a digital 130 nm CMOS process with no analog extensions and features high logic gate density of 150 kgates per mm/sup 2/. The transmitter architecture is based on an all-digital phase-locked loop (AD-PLL), which is built from the ground up using digital techniques that exploit high speed and high density of a deep-submicron CMOS process while avoiding its weaker handling of voltage resolution. We also present a high-performance flip-flop used in this design. It features low CLK-to-Q delay and negative setup time. Because the flip-flop is symmetrical along the vertical axis, the resolution window is symmetrical for rising and falling data transitions in the time-to-digital converter (TDC). The RF transmitter area occupies only 0.54 mm/sup 2/ and the current consumption is 49 mA at 1.5 V supply and 4 mW of RF output, and includes the companion DSP. This proves attractiveness and competitiveness of the "digital RF" approach whose goal is to replace RF functions with high-speed digital logic gates.