A 14-bit 20-Msamples/s pipelined A/D converter with high slewing amplifier

Abstract

This paper describes a 14-bit 20MSPS switched-capacitor pipelined ADC designed in a complementary SiGe/SOI bipolar process. It features an input-to-output class A/B operational amplifier designed to drive large sampling capacitors of 10 pF without consuming excessive power. Prototype implementation exhibits measured INL of +/- 2.0 LSB, DNL of +/- 0.5 LSB, SNR of 73 dB and SFDR of 85 dB with a 2 MHz input signal. Analog power dissipation at lowest amplifier bias setting is 390 mW with 5 V supply.