Impact of selective process bias (SPB) of interconnects on circuit delay

Abstract

Interconnect parasitics are playing an increasingly important role in circuit performance as we move into the nanometer era of semiconductor technology. Hence accounting for interconnect process effects such as selective process bias (SPB) is becoming important for accurate circuit performance simulations. In this paper, the impact of SPB on circuit delay is demonstrated by studying its effect on capacitance, resistance, ring oscillator speed, and delay of commonly used ASIC cells. Simulations with and without SPB and comparison to measurements of ring oscillator structures in 90 nm process technology show how accounting for SPB increases the accuracy in prediction of ring oscillator speed.