DSP-coupled 2.4 GHz RF transmitter in 130 nm CMOS

R. Staszewski, R. Staszweski, J. Wallberg, T. Jung, C. Hung, D. Leipold, K. Maggio, P. Balsara
{"title":"DSP-coupled 2.4 GHz RF transmitter in 130 nm CMOS","authors":"R. Staszewski, R. Staszweski, J. Wallberg, T. Jung, C. Hung, D. Leipold, K. Maggio, P. Balsara","doi":"10.1109/DCAS.2004.1360451","DOIUrl":null,"url":null,"abstract":"We present an IC chip that integrates a TMS320C54x DSP. which is commonly used in cellular phones, with a multiGHz digital RF transmitter that meets the Bluetooth specifications. The RF transmitter is tightly coupled with the DSP and is directly mapped to its address space. The transmitter architecture is based on an all-digital PLL, which is built from the ground up using digital techniques and digital creation flow that exploit high speed and high density of a deep-submicron CMOS process while avoiding its weaker handling of voltage. The frequency synthesizer features a wideband frequency modulation capability. Due to its programmability, flexibility and portability, the digital RF transmitter serves as a foundation of a digital radio processor (DRP). As part of the digital flow, the digitally-controlled oscillator (DCO) and a class-E power-amplifier are created as ASIC cells with digital I/O's. All digital blocks, including the 2.4 GHz logic, are synthesized from VHDL and auto routed. The use of VHDL allows for a tight and seamless integration of RF with the DSP. To take advantage of the direct DSP-RF coupling and to demonstrate a software-defined radio (SDR) capability, a DSP program is written to perform modulation of the GSM standard. The chip is fabricated in a baseline 130 nm CMOS process with no analog extensions.","PeriodicalId":185376,"journal":{"name":"Proceedings of the 2004 IEEE Dallas/CAS Workshop Implementation of High Performance Circuits","volume":"17 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 2004 IEEE Dallas/CAS Workshop Implementation of High Performance Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DCAS.2004.1360451","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3

Abstract

We present an IC chip that integrates a TMS320C54x DSP. which is commonly used in cellular phones, with a multiGHz digital RF transmitter that meets the Bluetooth specifications. The RF transmitter is tightly coupled with the DSP and is directly mapped to its address space. The transmitter architecture is based on an all-digital PLL, which is built from the ground up using digital techniques and digital creation flow that exploit high speed and high density of a deep-submicron CMOS process while avoiding its weaker handling of voltage. The frequency synthesizer features a wideband frequency modulation capability. Due to its programmability, flexibility and portability, the digital RF transmitter serves as a foundation of a digital radio processor (DRP). As part of the digital flow, the digitally-controlled oscillator (DCO) and a class-E power-amplifier are created as ASIC cells with digital I/O's. All digital blocks, including the 2.4 GHz logic, are synthesized from VHDL and auto routed. The use of VHDL allows for a tight and seamless integration of RF with the DSP. To take advantage of the direct DSP-RF coupling and to demonstrate a software-defined radio (SDR) capability, a DSP program is written to perform modulation of the GSM standard. The chip is fabricated in a baseline 130 nm CMOS process with no analog extensions.
dsp耦合2.4 GHz射频发射器在130纳米CMOS
提出了一种集成TMS320C54x DSP的集成电路芯片。它通常用于蜂窝电话,具有符合蓝牙规格的多ghz数字RF发射器。射频发射机与DSP紧密耦合,并直接映射到其地址空间。发射机架构基于全数字锁相环,采用数字技术和数字创建流程从头开始构建,利用深亚微米CMOS工艺的高速和高密度,同时避免其较弱的电压处理能力。频率合成器具有宽带调频能力。由于其可编程性、灵活性和便携性,数字射频发射机可作为数字无线电处理器(DRP)的基础。作为数字流程的一部分,数字控制振荡器(DCO)和e类功率放大器被创建为具有数字I/O的ASIC单元。包括2.4 GHz逻辑在内的所有数字块都是由VHDL合成并自动路由的。使用VHDL可以将RF与DSP紧密无缝集成。为了利用直接的DSP- rf耦合并演示软件定义无线电(SDR)能力,编写了一个DSP程序来执行GSM标准的调制。该芯片采用基准130纳米CMOS工艺制造,没有模拟扩展。
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