R. Staszewski, R. Staszweski, J. Wallberg, T. Jung, C. Hung, D. Leipold, K. Maggio, P. Balsara
{"title":"DSP-coupled 2.4 GHz RF transmitter in 130 nm CMOS","authors":"R. Staszewski, R. Staszweski, J. Wallberg, T. Jung, C. Hung, D. Leipold, K. Maggio, P. Balsara","doi":"10.1109/DCAS.2004.1360451","DOIUrl":null,"url":null,"abstract":"We present an IC chip that integrates a TMS320C54x DSP. which is commonly used in cellular phones, with a multiGHz digital RF transmitter that meets the Bluetooth specifications. The RF transmitter is tightly coupled with the DSP and is directly mapped to its address space. The transmitter architecture is based on an all-digital PLL, which is built from the ground up using digital techniques and digital creation flow that exploit high speed and high density of a deep-submicron CMOS process while avoiding its weaker handling of voltage. The frequency synthesizer features a wideband frequency modulation capability. Due to its programmability, flexibility and portability, the digital RF transmitter serves as a foundation of a digital radio processor (DRP). As part of the digital flow, the digitally-controlled oscillator (DCO) and a class-E power-amplifier are created as ASIC cells with digital I/O's. All digital blocks, including the 2.4 GHz logic, are synthesized from VHDL and auto routed. The use of VHDL allows for a tight and seamless integration of RF with the DSP. To take advantage of the direct DSP-RF coupling and to demonstrate a software-defined radio (SDR) capability, a DSP program is written to perform modulation of the GSM standard. The chip is fabricated in a baseline 130 nm CMOS process with no analog extensions.","PeriodicalId":185376,"journal":{"name":"Proceedings of the 2004 IEEE Dallas/CAS Workshop Implementation of High Performance Circuits","volume":"17 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 2004 IEEE Dallas/CAS Workshop Implementation of High Performance Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DCAS.2004.1360451","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
We present an IC chip that integrates a TMS320C54x DSP. which is commonly used in cellular phones, with a multiGHz digital RF transmitter that meets the Bluetooth specifications. The RF transmitter is tightly coupled with the DSP and is directly mapped to its address space. The transmitter architecture is based on an all-digital PLL, which is built from the ground up using digital techniques and digital creation flow that exploit high speed and high density of a deep-submicron CMOS process while avoiding its weaker handling of voltage. The frequency synthesizer features a wideband frequency modulation capability. Due to its programmability, flexibility and portability, the digital RF transmitter serves as a foundation of a digital radio processor (DRP). As part of the digital flow, the digitally-controlled oscillator (DCO) and a class-E power-amplifier are created as ASIC cells with digital I/O's. All digital blocks, including the 2.4 GHz logic, are synthesized from VHDL and auto routed. The use of VHDL allows for a tight and seamless integration of RF with the DSP. To take advantage of the direct DSP-RF coupling and to demonstrate a software-defined radio (SDR) capability, a DSP program is written to perform modulation of the GSM standard. The chip is fabricated in a baseline 130 nm CMOS process with no analog extensions.