Clocking and synchronization in sub-90 nm system-on-chip (SoC) designs

Abstract

Sub-90 nm designs create many challenging problems for VLSI designers. A key challenge is the unpredictable behavior of the interconnect characteristics resulting in delay variations. New techniques such as current-mode interconnection scheme and results from other circuit domain could be helpful in dealing with this problem. Also, prevention and correction both should be considered in achieving signal and function integrity. This article presents some solutions for the clocking and synchronization problem for the design of SoCs specifically in asynchronous design, GALS, and current-mode interconnects.