A gate leakage reduction strategy for sub-70 nm memory circuits

Abstract

The gate oxide thickness in sub-70 nm process technologies approaches the limit where direct gate tunneling current starts to play a significant role in both off-state and on-state transistor operating modes. This gate leakage current, in addition to sub-threshold leakage, results in dramatic increase in total leakage power. Hence, efficient leakage reduction strategies that address the different dominant leakage components are necessary. In this paper, we analyze the use of NC-SRAM memory cell for its effectiveness in gate leakage reduction. The technique provided around 60% gate leakage savings in 65 nm technology with minimal impact on area, as compared to a conventional SRAM.