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[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design最新文献

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ATPG with efficient testability measures and partial fault simulation ATPG具有有效的可测试性措施和部分故障仿真
[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design Pub Date : 1991-01-04 DOI: 10.1109/ISVD.1991.185089
K. Jain, J. Jacob, M. Srinivas
{"title":"ATPG with efficient testability measures and partial fault simulation","authors":"K. Jain, J. Jacob, M. Srinivas","doi":"10.1109/ISVD.1991.185089","DOIUrl":"https://doi.org/10.1109/ISVD.1991.185089","url":null,"abstract":"Proposes an improved version of the test generation algorithm PODEM path oriented decision-making incorporating a different technique for backtracing and forward implication. The authors also propose a partial fault simulator which is integrated into the improved PODEM algorithm. The performance of this test generation package (when partial fault simulator is employed) is compared to that of a concurrent fault simulator using deterministically generated test patterns. It is shown that the runtime performance of the algorithm compares favourably with that of the concurrent fault simulator and is less memory intensive. The authors also present effective heuristics to determine some of the redundant faults and to drive the test vectors for some PI faults, by the use of implication relations. Experimental results on all the 10 ISCAS benchmark circuits demonstrate that the algorithm is faster and more efficient than the PODEM algorithm for these circuits.<<ETX>>","PeriodicalId":183602,"journal":{"name":"[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design","volume":"135 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124237902","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A systolic chip for LZ based data compression 一种基于LZ的数据压缩收缩芯片
[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design Pub Date : 1991-01-04 DOI: 10.1109/ISVD.1991.185144
N. Ranganathan, S. Henriques
{"title":"A systolic chip for LZ based data compression","authors":"N. Ranganathan, S. Henriques","doi":"10.1109/ISVD.1991.185144","DOIUrl":"https://doi.org/10.1109/ISVD.1991.185144","url":null,"abstract":"The authors describe the design of a systolic VLSI chip which implements the LZ technique for data compression. The LZ-based compression method due to Lempel and Ziv (1977) is a very powerful technique and gives very high compression efficiency for text as well as image data. The architecture is systolic and uses the principles of pipelining and parallelism in order to obtain high speed and throughput. The order of complexity of the computations is reduced from n/sup 2/ to n. The chip can be integrated into real time systems so that data can be compressed and decompressed on-the-fly. A prototype CMOS compression chip implementing a systolic array of 9 processors has been designed and verified and currently, is being fabricated. The chip is expected to operate at 20 MHz and yield a compression rate of about 20 million characters per second.<<ETX>>","PeriodicalId":183602,"journal":{"name":"[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126843129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A simulated annealing based state assignment approach for control synthesis 一种基于模拟退火的状态分配控制综合方法
[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design Pub Date : 1991-01-04 DOI: 10.1109/ISVD.1991.185091
B. Mitra, S. Jha, P.P. Choudhuri
{"title":"A simulated annealing based state assignment approach for control synthesis","authors":"B. Mitra, S. Jha, P.P. Choudhuri","doi":"10.1109/ISVD.1991.185091","DOIUrl":"https://doi.org/10.1109/ISVD.1991.185091","url":null,"abstract":"The optimality of synthesized control designs for complex VLSI systems hinges to a great extent on the efficiency of the state assignment phase. A new system is presented for state assignment of sequential functions modelled as finite state machines. Using a simulated annealing technique and an embedded mechanism to vary the state assignment length, this scheme arrives at a synthesized logic that is efficient in terms of area occupied by both the memory elements and the combinational logic. This is in contrast to most existing methods for state assignment that use minimum code length to ensure least cost of sequential logic. Appropriate annealing schedules, perturbation functions and grouping of state codes for efficient state assignment have been arrived at. The authors present results that indicate that it is possible to achieve significant improvements in both the area and delay of the combinational logic by increasing the code length. A mechanism has also been incorporated in the system for expert designers to specify their own state assignments. Developed at Texas Instruments, this technique has been found to give encouraging results on several large and realistic designs.<<ETX>>","PeriodicalId":183602,"journal":{"name":"[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133797589","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Signal delay in linear leaky RC mesh/tree 线性泄漏RC网格/树的信号延迟
[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design Pub Date : 1991-01-04 DOI: 10.1109/ISVD.1991.185116
N. K. Jain, V. Prasad, A. Bhattacharyya
{"title":"Signal delay in linear leaky RC mesh/tree","authors":"N. K. Jain, V. Prasad, A. Bhattacharyya","doi":"10.1109/ISVD.1991.185116","DOIUrl":"https://doi.org/10.1109/ISVD.1991.185116","url":null,"abstract":"As chip dimensions are reduced, the performance of integrated circuits is limited by the delays associated with the interconnections. For the purpose of propagation delay estimation in digital circuits, these interconnections can be modelled by leaky RC tree/line/mesh. Signal delay in a nonleaky RC tree can be estimated by a tree algorithm. In this paper a modified tree algorithm (linear order) is presented for estimating signal delay in a leaky RC tree with nonzero initial conditions.<<ETX>>","PeriodicalId":183602,"journal":{"name":"[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design","volume":"418 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124254992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A switched capacitor filter synthesis system with built-in design for manufacturability 一种内置可制造性设计的开关电容滤波综合系统
[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design Pub Date : 1991-01-04 DOI: 10.1109/ISVD.1991.185106
M. Mehendale
{"title":"A switched capacitor filter synthesis system with built-in design for manufacturability","authors":"M. Mehendale","doi":"10.1109/ISVD.1991.185106","DOIUrl":"https://doi.org/10.1109/ISVD.1991.185106","url":null,"abstract":"The paper presents a switched capacitor filter synthesis system with yield estimation and optimization as the integral components of the design environment. The design process is an iterative process involving filter synthesis and yield estimation. Different design choices such as filter order, approximation, circuit topology, etc., affect the yield and also other parameters such as filter area, noise and dynamic range. The integrated environment offers effective mechanisms for exploring the design decision space to achieve the optimum in terms of yield and other design considerations. The paper describes the filter synthesis, yield estimation and optimization aspects of the system. The capabilities offered in the areas of data and flow management are also discussed. The results for a low pass filter design are presented.<<ETX>>","PeriodicalId":183602,"journal":{"name":"[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122908258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
CLSS-a workbench for control logic synthesis 用于控制逻辑综合的工作台
[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design Pub Date : 1991-01-04 DOI: 10.1109/ISVD.1991.185120
B. Mitra, L. Ramachandran, S. Rajam, G. Rajagopalan
{"title":"CLSS-a workbench for control logic synthesis","authors":"B. Mitra, L. Ramachandran, S. Rajam, G. Rajagopalan","doi":"10.1109/ISVD.1991.185120","DOIUrl":"https://doi.org/10.1109/ISVD.1991.185120","url":null,"abstract":"Describes a system called CLSS, that serves as a workbench for the synthesis of control logic. The system provides an integrated solution to the designer by providing effective solutions for all the major steps in the control logic synthesis flow. CLSS allows specification of the control logic in the form of a state transition representation. Through a set of transformation steps, all of which are an integral part of the CLSS workbench, the layout of the design is generated for standard cell or PLA based implementations. In addition to providing automated solutions to optimally perform state assignment, logic minimization, constrained area-delay optimization, etc., CLSS provides a mechanism for the expert designers to override the decisions taken by the system. The major strength of the system lies in the tight coupling between the several components of the flow in an integrated environment. Designed at Texas Instruments, the CLSS workbench has been successfully used on several large and realistic designs.<<ETX>>","PeriodicalId":183602,"journal":{"name":"[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127233225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
On reducing test length in LFSR based testing 基于LFSR的测试中缩短测试长度的研究
[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design Pub Date : 1991-01-04 DOI: 10.1109/ISVD.1991.185122
S. Mukund, T. Rao, K. Zeng
{"title":"On reducing test length in LFSR based testing","authors":"S. Mukund, T. Rao, K. Zeng","doi":"10.1109/ISVD.1991.185122","DOIUrl":"https://doi.org/10.1109/ISVD.1991.185122","url":null,"abstract":"Proposes a new method for generating test patterns in the BIT (built-in testing) environment. This method reduces the testing time under both deterministic and pseudo-random testing, for a desired fault coverage. It relies on the fact that the LFSR (linear feedback shift register) sequence is deterministic. Since the position of any test vector in this sequence can be predicted, the starting vectors (seeds) can be rightly chosen and thereby obtain maximal number of test vectors in minimal time. However, even for reasonably long LFSRs, the length of the sequence can be exorbitantly large, rendering it impractical to search the whole length. The authors propose a technique to overcome this problem, and predict the position of a test vector in the LFSR sequence, in a computationally feasible manner.<<ETX>>","PeriodicalId":183602,"journal":{"name":"[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123349913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Automated data path synthesis to avoid global interconnects 自动数据路径合成，避免全局互连
[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design Pub Date : 1991-01-04 DOI: 10.1109/ISVD.1991.185085
V. K. Raj, C.S. Patwardhan
{"title":"Automated data path synthesis to avoid global interconnects","authors":"V. K. Raj, C.S. Patwardhan","doi":"10.1109/ISVD.1991.185085","DOIUrl":"https://doi.org/10.1109/ISVD.1991.185085","url":null,"abstract":"Incorporates into a behavioral synthesis system an algorithm to minimize global interconnects in the data path. In order to accomplish this, the authors define a model of the data path to almost completely avoid global interconnects. In this approach, they pay the penalty of extra registers and extra microinstructions to avoid global interconnects. The proposed model of the data path results in large area savings in behavioral synthesis.<<ETX>>","PeriodicalId":183602,"journal":{"name":"[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128463932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
PLATEST: A PLA test generator PLATEST: PLA测试发生器
[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design Pub Date : 1991-01-04 DOI: 10.1109/ISVD.1991.185137
T. Raghuram, M. Hasan
{"title":"PLATEST: A PLA test generator","authors":"T. Raghuram, M. Hasan","doi":"10.1109/ISVD.1991.185137","DOIUrl":"https://doi.org/10.1109/ISVD.1991.185137","url":null,"abstract":"The growing use of PLAs in VLSI chips makes it imperative to have detailed study of the physical failures and the test generation. In this paper, physical failure analysis is carried out for NMOS PLA using SPICE simulation and the effects on the output of the PLA are studied. This study would be helpful in fault diagnosis and in improved design of the PLA. Based on these results the fault models are analysed and a novel test pattern generator, PLATEST, has been developed to generate minimal test set. PLATEST generates tests for all detectable cross-point faults and bridging faults. PLATEST has been implemented on a PC-AT in C(DOS).<<ETX>>","PeriodicalId":183602,"journal":{"name":"[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129422204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Method for testable design and for built-in test 可测试设计和内置测试方法
[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design Pub Date : 1991-01-04 DOI: 10.1109/ISVD.1991.185136
P. Petrov
{"title":"Method for testable design and for built-in test","authors":"P. Petrov","doi":"10.1109/ISVD.1991.185136","DOIUrl":"https://doi.org/10.1109/ISVD.1991.185136","url":null,"abstract":"The author proposes a method for testable design and for built-in test based on introduction of a new logical value in logic circuits. It is proved that only one (i) test is needed for detecting all constant multiple s-a-0/1 faults in any combinational (synchronous sequential) circuit where i is maximum sequential depth (MSD) of that circuit.<<ETX>>","PeriodicalId":183602,"journal":{"name":"[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design","volume":"184 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125834888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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