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[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design最新文献

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Partitioning and reorganization of hierarchical circuits for DFT DFT中层次电路的划分与重组
[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design Pub Date : 1991-01-04 DOI: 10.1109/ISVD.1991.185101
R. Gupta, R. Srinivasan, M. Breuer
{"title":"Partitioning and reorganization of hierarchical circuits for DFT","authors":"R. Gupta, R. Srinivasan, M. Breuer","doi":"10.1109/ISVD.1991.185101","DOIUrl":"https://doi.org/10.1109/ISVD.1991.185101","url":null,"abstract":"To make VLSI circuits more testable, design-for-testability (DFT) and built-in self-test (BIST) techniques are often employed. These techniques typically assume a register/gate level decomposition of the overall circuit. In general, the given user hierarchy is not appropriate for embedding various testable design methodologies (TDMs). This paper describes a new canonical partitioning of a circuit into disjoint subcircuits, referred to as clouds and registers. A salient feature of this partitioning is the attempt to preserve the user hierarchy as much as possible. This enables easy identification of equivalence among various clouds of the circuit. The authors also show how this canonical partitioning can be used for three specific TDMs, namely full scan, partial scan and BILBO designs. For the case of full scan, deterministic tests are generated for one cloud in each equivalence class, and replicated for all clouds in that class. These tests are organized to form a test set for the entire circuit. Test vectors are edited to correspond to the order of flip-flops in the scan paths of the circuit. Analytical expressions for the reduction in the number of test vectors due to this canonical partitioning are derived and substantiated with experimental results.<<ETX>>","PeriodicalId":183602,"journal":{"name":"[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design","volume":"168 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115987995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A new approach for multilevel logic cell optimization 一种多层逻辑单元优化的新方法
[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design Pub Date : 1991-01-04 DOI: 10.1109/ISVD.1991.185099
P. Poechmueller, M. Glesner
{"title":"A new approach for multilevel logic cell optimization","authors":"P. Poechmueller, M. Glesner","doi":"10.1109/ISVD.1991.185099","DOIUrl":"https://doi.org/10.1109/ISVD.1991.185099","url":null,"abstract":"Presents new ideas in the field of multi-level logic optimization for automatic logic macrocell synthesis. A new approach is proposed which performs a quasi-parallel optimization of very different and complex tasks via a simulated annealing based expert system. A first working prototype software package for multilevel logic cell optimization had been implemented to prove the validity of this approach. The system performs a real architecture exploration, finding the best solution with respect to a certain cost-function which takes into account actual design parameters like speed, area, power, and not only indirect parameters like number of literals etc. Another feature is the small and primitive set of required rules.<<ETX>>","PeriodicalId":183602,"journal":{"name":"[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123201817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Monte Carlo simulation environment for wear out in VLSI systems VLSI系统损耗的蒙特卡罗模拟环境
[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design Pub Date : 1991-01-04 DOI: 10.1109/ISVD.1991.185125
G. Choi, R. K. Iyer, J. Patel
{"title":"A Monte Carlo simulation environment for wear out in VLSI systems","authors":"G. Choi, R. K. Iyer, J. Patel","doi":"10.1109/ISVD.1991.185125","DOIUrl":"https://doi.org/10.1109/ISVD.1991.185125","url":null,"abstract":"The authors describe a simulation environment for reliability prediction of VLSI designs. Specifically, the effect of electromigration on the time-to-failure is investigated. The capabilities of the environment are illustrated with a case study of a microprocessor intended for control applications. The system under investigation is first simulated at the switch level and trace data on the switching activity is collected. This data is then used along with Monte Carlo simulation to model wear-out at the chip-level.<<ETX>>","PeriodicalId":183602,"journal":{"name":"[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design","volume":"140 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123373108","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A neural network for channel routing 信道路由的神经网络
[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design Pub Date : 1991-01-04 DOI: 10.1109/ISVD.1991.185131
Pao-Hsu Shih, Wu-Shung Feng
{"title":"A neural network for channel routing","authors":"Pao-Hsu Shih, Wu-Shung Feng","doi":"10.1109/ISVD.1991.185131","DOIUrl":"https://doi.org/10.1109/ISVD.1991.185131","url":null,"abstract":"The authors propose a neural network to handle the channel routing problem. This network also allows the user to preroute critical nets and then invoke the network to complete the rest. Typical examples from published literature are taken for experiments. The theoretic lower bounds are achieved in all examples.<<ETX>>","PeriodicalId":183602,"journal":{"name":"[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114199293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An efficient interchangeable switch-box router: a generalized study 一种高效的可互换开关箱路由器:概论研究
[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design Pub Date : 1991-01-04 DOI: 10.1109/ISVD.1991.185132
R. K. Pal, A. Pal
{"title":"An efficient interchangeable switch-box router: a generalized study","authors":"R. K. Pal, A. Pal","doi":"10.1109/ISVD.1991.185132","DOIUrl":"https://doi.org/10.1109/ISVD.1991.185132","url":null,"abstract":"The authors present a new algorithm for routing a reserved two-layer switch-box with interchangeable terminals. Savings in respect of number(s) of horizontal and/or vertical movements and number of via holes used are achieved by simply interchanging terminals in each cell.<<ETX>>","PeriodicalId":183602,"journal":{"name":"[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117235576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The high level design of the long accumulator chip 长蓄能器芯片的高级设计
[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design Pub Date : 1991-01-04 DOI: 10.1109/ISVD.1991.185142
H. Fleurkens, R. Tangelder
{"title":"The high level design of the long accumulator chip","authors":"H. Fleurkens, R. Tangelder","doi":"10.1109/ISVD.1991.185142","DOIUrl":"https://doi.org/10.1109/ISVD.1991.185142","url":null,"abstract":"The authors discuss an architecture and its high level description of a long accumulator chip suited for the exact calculation of the inner products of floating point numbers. A highly parallel implementation is developed using eight independent adder stations, which add products to two circular long accumulators. A dispatcher schedules each product to the best available station. To validate this architecture and to calculate its performance, a high level description is created. This description is made with ESCHER+, an interactive schematic entry tool with a built-in simulator. The resulting description showed to be the basis for the further implementation of the chip.<<ETX>>","PeriodicalId":183602,"journal":{"name":"[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125713601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Tools for reliable software design of VLSI VLSI可靠软件设计工具
[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design Pub Date : 1991-01-04 DOI: 10.1109/ISVD.1991.185145
T.A. Silayeva
{"title":"Tools for reliable software design of VLSI","authors":"T.A. Silayeva","doi":"10.1109/ISVD.1991.185145","DOIUrl":"https://doi.org/10.1109/ISVD.1991.185145","url":null,"abstract":"The automation tools for reliable software design of VLSI are proposed. They consist of tools for program testing based on building the minimum coverage of the analyzed program's graph, and tools for providing the required reliability of a program during its execution based on optimum program redundancy.<<ETX>>","PeriodicalId":183602,"journal":{"name":"[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121244436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Compacting dead space in partitioning methods for random cells placements 随机单元格放置分区方法中的死区压缩
[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design Pub Date : 1991-01-04 DOI: 10.1109/ISVD.1991.185129
Y. Moon, W.T. Li, K.H. Lee
{"title":"Compacting dead space in partitioning methods for random cells placements","authors":"Y. Moon, W.T. Li, K.H. Lee","doi":"10.1109/ISVD.1991.185129","DOIUrl":"https://doi.org/10.1109/ISVD.1991.185129","url":null,"abstract":"The partitioning methods for placement work by allocating cells to partition groups. The groups are then further partitioned until the number of cells allocated to each group is small enough to be handled efficiently by other placement methods. The authors introduce extended channel constraint (ECC) graphs, a concept extended from Lauther's channel constraint graphs. The ECC graphs lead to a methodology for compacting and reorganizing dead space generated from the partitioning methods.<<ETX>>","PeriodicalId":183602,"journal":{"name":"[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131900230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design and performance evaluation of high-resolution oversampling A/D converters 高分辨率过采样A/D转换器的设计与性能评价
[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design Pub Date : 1991-01-04 DOI: 10.1109/ISVD.1991.185141
V. Dias, F. Maloberti
{"title":"Design and performance evaluation of high-resolution oversampling A/D converters","authors":"V. Dias, F. Maloberti","doi":"10.1109/ISVD.1991.185141","DOIUrl":"https://doi.org/10.1109/ISVD.1991.185141","url":null,"abstract":"An approach to the behavioural simulation of Sigma Delta A/D converters is presented. Integrator, comparator and digital filtering blocks are implemented with the advantage of being easily interfaced with component designers. Post-processing algorithms for overall performance evaluation are also discussed, specially by focusing on the fact they can largely affect the meaning of the results. Simulation results are presented that confirm the suitability of the proposed simulator and models.<<ETX>>","PeriodicalId":183602,"journal":{"name":"[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122864695","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Synthesis of a control unit from instruction set specification in VHDL environment 在VHDL环境下从指令集规范合成一个控制单元
[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design Pub Date : 1991-01-04 DOI: 10.1109/ISVD.1991.185117
K.R. Muralidhar, H. N. Mahabala
{"title":"Synthesis of a control unit from instruction set specification in VHDL environment","authors":"K.R. Muralidhar, H. N. Mahabala","doi":"10.1109/ISVD.1991.185117","DOIUrl":"https://doi.org/10.1109/ISVD.1991.185117","url":null,"abstract":"Automated design of control structures for digital systems has been one of the active areas of research in high level synthesis. This paper proposes a methodology for specifying an instruction set in VHDL and also presents a system for synthesizing controller for the target processor. The goal of this system is to serve as a tool to help in early evaluation of instruction sets for implementation in a processor design environment. The system accepts the instruction set specification and a microarchitecture description and generates a finite state machine controller. A suitable subset of VHDL has been defined for easy specification of instruction set. Facilities have also been provided to define system timings and to specify clock synchronous activities of the processor. The output is given in VTI FSM compiler format for further processing to generate PLA or standard cell implementation of the controller.<<ETX>>","PeriodicalId":183602,"journal":{"name":"[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130882090","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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