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[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design最新文献

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A practical approach to synchronous hardware verification 同步硬件验证的实用方法
[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design Pub Date : 1991-01-04 DOI: 10.1109/ISVD.1991.185114
G. Gopalakrishnan, P. Jain
{"title":"A practical approach to synchronous hardware verification","authors":"G. Gopalakrishnan, P. Jain","doi":"10.1109/ISVD.1991.185114","DOIUrl":"https://doi.org/10.1109/ISVD.1991.185114","url":null,"abstract":"Hardware designs expressed in a simple hardware description language can be formally verified by adapting techniques developed for software verification. This paper presents a case study that supports this claim. From the structural specification of a two-phase clocked synchronous hardware design, a behavioral description is automatically inferred. This is subject to algebraic simplification using rewrite rules. Some of the simplification steps are achieved by discovering a loop invariant associated with a loop in the control flow graph. Once simplified, a homomorphism is exhibited from the implementation algebra to the specification algebra, to complete the proof.<<ETX>>","PeriodicalId":183602,"journal":{"name":"[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127089019","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Multilevel simulation tool for designing fault-tolerant VLSI array processors 设计容错VLSI阵列处理器的多级仿真工具
[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design Pub Date : 1991-01-04 DOI: 10.1109/ISVD.1991.185139
P. Poechmueller, G. Sharma, M. Glesner
{"title":"Multilevel simulation tool for designing fault-tolerant VLSI array processors","authors":"P. Poechmueller, G. Sharma, M. Glesner","doi":"10.1109/ISVD.1991.185139","DOIUrl":"https://doi.org/10.1109/ISVD.1991.185139","url":null,"abstract":"The authors present the design details of an integrated CAD tool for efficient realization of parallel processors for high throughput in real-time digital signal processing (DSP) applications. The array specification language of this tool allows VLSI designer to specify the input at dependence graph, signal flow graph and processor architecture-level. Core of this tool is a functional-structural simulator which is embedded into an environment supporting array processor design. One of the most important features of this CAD tool is that advanced fault-tolerance techniques can be incorporated in an early design phase not only to achieve high reliability and long life time but also to enhance production yields.<<ETX>>","PeriodicalId":183602,"journal":{"name":"[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design","volume":"126 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134476788","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A novel technique for folding logic arrays 一种新的逻辑阵列折叠技术
[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design Pub Date : 1991-01-04 DOI: 10.1109/ISVD.1991.185100
L. N. Kannan, D. Sarma
{"title":"A novel technique for folding logic arrays","authors":"L. N. Kannan, D. Sarma","doi":"10.1109/ISVD.1991.185100","DOIUrl":"https://doi.org/10.1109/ISVD.1991.185100","url":null,"abstract":"The folding of logic arrays is a technique to reduce the area of the array by exploiting its sparsity. Since the problem is NP-complete, heuristic algorithms that yield a near optimal solution have to be employed. In this paper the array optimization problem has been studied and a method employing a combination of simulated annealing and heuristic algorithms has been developed to find a near optimal solution for both simple and multiple folding of logic arrays. The algorithms developed have been implemented in a computer program called GAMIN-SA. When compared to PLEASURE, GAMIN-SA was seen to perform as good or better with regard to quality of solution and, for the bigger PLAs (multiple folding), it was better in terms of run-time as well.<<ETX>>","PeriodicalId":183602,"journal":{"name":"[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115837505","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Linear ordering by stochastic evolution 随机进化的线性排序
[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design Pub Date : 1991-01-04 DOI: 10.1109/ISVD.1991.185105
Y. Saab, V. Rao
{"title":"Linear ordering by stochastic evolution","authors":"Y. Saab, V. Rao","doi":"10.1109/ISVD.1991.185105","DOIUrl":"https://doi.org/10.1109/ISVD.1991.185105","url":null,"abstract":"Linear ordering has applications in standard cells and gate array placement. This paper presents a new approach to linear ordering based on the new stochastic evolution (SE) methodology for solving intractable combinatorial optimization problems. The SE heuristic performs better than Kang's heuristic and simulated annealing. In many cases, the SE heuristic was significantly better than Kang's heuristic, and an order of magnitude better than simulated annealing.<<ETX>>","PeriodicalId":183602,"journal":{"name":"[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127189318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Development of TTL equivalent library for ASIC design tools and its use to design printer adapter interface ASIC 开发用于ASIC设计工具的TTL等效库，并将其用于设计打印机适配器接口的ASIC
[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design Pub Date : 1991-01-04 DOI: 10.1109/ISVD.1991.185134
S. Shukla, S. K. David, A. Shaligram
{"title":"Development of TTL equivalent library for ASIC design tools and its use to design printer adapter interface ASIC","authors":"S. Shukla, S. K. David, A. Shaligram","doi":"10.1109/ISVD.1991.185134","DOIUrl":"https://doi.org/10.1109/ISVD.1991.185134","url":null,"abstract":"The authors describe development of TE74XX (TTL functional equivalent) library cells for ASIC design tools on Sun SPARCStation1 (model14/110). The functionality of TE74XX series cells is confirmed through exhaustive simulation using mixed-mode simulator VTISim and complete documentation is prepared. Applicability of TE74XX library is demonstrated by designing a 40-pin PAI (Printer Adapter Interface) ASIC ('ES9001').<<ETX>>","PeriodicalId":183602,"journal":{"name":"[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124931522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
YAQT: Yet another quad tree 又一棵四轴树
[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design Pub Date : 1991-01-04 DOI: 10.1109/ISVD.1991.185143
P.V. Srinivas, V.K. Dwivedi
{"title":"YAQT: Yet another quad tree","authors":"P.V. Srinivas, V.K. Dwivedi","doi":"10.1109/ISVD.1991.185143","DOIUrl":"https://doi.org/10.1109/ISVD.1991.185143","url":null,"abstract":"A new data structure for storing two dimensional objects has been presented. A multiple storage quad tree is a quad tree which stores pointers to objects intersecting more than one quad in all of the quad that they intersect. The YAQT (Yet Another Quad Tree) is a modified form of multiple storage quad tree with no list required for storing crossing objects. A substantial improvement in the region query operation and tree traversal has been obtained. On the other hand only an insignificant increase of memory requirement is noticed in practical situations. Finally the YAQT and the algorithms which operate on it are found to be very simple.<<ETX>>","PeriodicalId":183602,"journal":{"name":"[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121603740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Generic component library characterization for high level synthesis 用于高级合成的通用组件库表征
[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design Pub Date : 1991-01-04 DOI: 10.1109/ISVD.1991.185084
N. Dutt
{"title":"Generic component library characterization for high level synthesis","authors":"N. Dutt","doi":"10.1109/ISVD.1991.185084","DOIUrl":"https://doi.org/10.1109/ISVD.1991.185084","url":null,"abstract":"Describes a novel generator-generator environment for characterizing generic component libraries used in high level hardware synthesis. The environment is composed of LEGEND, a language used to specify generic libraries, and GENUS, the generated generic component library. GENUS provides generic component instances for the task of behavior-to-structure mapping in high level synthesis. The LEGEND/GENUS environment complements a language such as VHDL by providing component library generator-generators with behavioral models for simulation and subsequent synthesis. The LEGEND language has a simple and extensible syntax which allows users to add and modify component generators easily. Generic components in GENUS have realistic register transfer semantics, including clocking, asynchrony and data bi-directionality. The LEGEND/GENUS environment is implemented on SUN workstations in C/Unix and is used by a suite of behavioral and logic synthesis tools at U.C. Irvine.<<ETX>>","PeriodicalId":183602,"journal":{"name":"[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130757451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Methods for computer estimation of word lengths for behaviorally synthesized digital ASICs 行为合成数字专用集成电路字长计算机估计方法
[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design Pub Date : 1991-01-04 DOI: 10.1109/ISVD.1991.185086
Y. Kumar, J. Knight
{"title":"Methods for computer estimation of word lengths for behaviorally synthesized digital ASICs","authors":"Y. Kumar, J. Knight","doi":"10.1109/ISVD.1991.185086","DOIUrl":"https://doi.org/10.1109/ISVD.1991.185086","url":null,"abstract":"In digital ASICs with predefined algorithms, the optimal word length can be defined for each internal operator, bus and register, based on the accuracy needed at the ASIC outputs. If optimal word lengths are used, rather than merely choosing 8, 16 or 32 bits, then considerable silicon area may be saved. This paper describes methods of optimizing these word lengths in a form suitable for use by a behavioral circuit-synthesis program. The estimates are based on methods used in control systems and digital filters. Methods are described for circuits which may have nonlinearities but do not contain nonlinearities within feedback loops.<<ETX>>","PeriodicalId":183602,"journal":{"name":"[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design","volume":"202 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132347077","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Simulator for IDEAL-implementation and environment 用于理想实现和环境的模拟器
[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design Pub Date : 1991-01-04 DOI: 10.1109/ISVD.1991.185115
R. Parekhji, G. Venkatesh, S. Sherlekar, S. Biswas
{"title":"Simulator for IDEAL-implementation and environment","authors":"R. Parekhji, G. Venkatesh, S. Sherlekar, S. Biswas","doi":"10.1109/ISVD.1991.185115","DOIUrl":"https://doi.org/10.1109/ISVD.1991.185115","url":null,"abstract":"Presents the simulation strategy for a new hardware description language, IDEAL. IDEAL supports hierarchical and modular descriptions of asynchronous and synchronous digital systems in terms of behaviours and structures. It forms the basis of the IDEAS project for VLSI CAD tools development. The simulator for IDEAL is based on the coroutine model. A design in IDEAL is simulated by appropriately scheduling coroutines corresponding to the design entities. The behavioral and structural description is translated into coroutines by compiling IDEAL data transfer and control constructs into 'C'. The semantics of IDEAL constructs are discussed and the simulator implementation and supporting environment are described.<<ETX>>","PeriodicalId":183602,"journal":{"name":"[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132362853","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Can test length be reduced during synthesis process? 在合成过程中测试长度可以缩短吗?
[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design Pub Date : 1991-01-04 DOI: 10.1109/ISVD.1991.185093
K. De, P. Banerjee
{"title":"Can test length be reduced during synthesis process?","authors":"K. De, P. Banerjee","doi":"10.1109/ISVD.1991.185093","DOIUrl":"https://doi.org/10.1109/ISVD.1991.185093","url":null,"abstract":"Conventional multi-level logic synthesis is targeted to reduce the area of the logic circuits (estimated via literal count). This paper looks at multi-level combinational logic synthesis from the objective of minimizing test length, i.e. the size of a test set to detect all irredundant single stuck-at faults in the circuit. The length of a test set affects the test application cost. The synthesis process has been modified to obtain circuits that can be tested with smaller test length. Results of the implementation have shown significant reduction in test length with little increase in run time over the MIS-II synthesis system and very little increase in literal count.<<ETX>>","PeriodicalId":183602,"journal":{"name":"[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114341180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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