Methods for computer estimation of word lengths for behaviorally synthesized digital ASICs

Abstract

In digital ASICs with predefined algorithms, the optimal word length can be defined for each internal operator, bus and register, based on the accuracy needed at the ASIC outputs. If optimal word lengths are used, rather than merely choosing 8, 16 or 32 bits, then considerable silicon area may be saved. This paper describes methods of optimizing these word lengths in a form suitable for use by a behavioral circuit-synthesis program. The estimates are based on methods used in control systems and digital filters. Methods are described for circuits which may have nonlinearities but do not contain nonlinearities within feedback loops.<>