设计容错VLSI阵列处理器的多级仿真工具

[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design Pub Date : 1991-01-04 DOI:10.1109/ISVD.1991.185139

P. Poechmueller, G. Sharma, M. Glesner

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引用次数: 0

摘要

作者介绍了一种集成CAD工具的设计细节，该工具可以有效地实现实时数字信号处理(DSP)应用中的高吞吐量并行处理器。该工具的阵列规范语言允许VLSI设计人员在依赖图、信号流图和处理器架构级指定输入。该工具的核心是一个功能结构模拟器，该模拟器嵌入到支持阵列处理器设计的环境中。该CAD工具最重要的特点之一是先进的容错技术可以在早期设计阶段纳入，不仅可以实现高可靠性和长寿命，还可以提高产量

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Multilevel simulation tool for designing fault-tolerant VLSI array processors

The authors present the design details of an integrated CAD tool for efficient realization of parallel processors for high throughput in real-time digital signal processing (DSP) applications. The array specification language of this tool allows VLSI designer to specify the input at dependence graph, signal flow graph and processor architecture-level. Core of this tool is a functional-structural simulator which is embedded into an environment supporting array processor design. One of the most important features of this CAD tool is that advanced fault-tolerance techniques can be incorporated in an early design phase not only to achieve high reliability and long life time but also to enhance production yields.<>

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[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design

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