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[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design最新文献

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Pipelined concurrent simulation on distributed-memory parallel computers 分布式内存并行计算机上的流水线并行仿真
[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design Pub Date : 1991-01-04 DOI: 10.1109/ISVD.1991.185094
Shang-E Tai, D. Bhattacharya
{"title":"Pipelined concurrent simulation on distributed-memory parallel computers","authors":"Shang-E Tai, D. Bhattacharya","doi":"10.1109/ISVD.1991.185094","DOIUrl":"https://doi.org/10.1109/ISVD.1991.185094","url":null,"abstract":"Presents a space- and time-efficient approach to fault simulation on distributed-memory message-passing parallel computers. The processors in the parallel machine, and the host, communicate in a pipelined fashion where each processor simulates only one partition of the circuit under consideration using the concurrent simulation approach. If good load balancing can be obtained, this approach leads to nearly linear speedup when a large number of vectors are simulated. Further, practical implementations of this approach uses memory in the parallel machine efficiently. A preliminary implementation of this approach on an Intel hypercube machine is then described. Experimental results obtained using the ISCAS85 benchmark circuits confirm the prediction that the actual speedup is primarily dependent on the load distribution across processors. Further, simple circuit partitioning heuristic is seen to provide moderate to good speedup in most cases.<<ETX>>","PeriodicalId":183602,"journal":{"name":"[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133343766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A novel integrated scheduling and allocation algorithm for data path synthesis 一种新的数据路径综合调度与分配算法
[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design Pub Date : 1991-01-04 DOI: 10.1109/ISVD.1991.185119
A. Kumar, A. Kumar, M. Balakrishnan
{"title":"A novel integrated scheduling and allocation algorithm for data path synthesis","authors":"A. Kumar, A. Kumar, M. Balakrishnan","doi":"10.1109/ISVD.1991.185119","DOIUrl":"https://doi.org/10.1109/ISVD.1991.185119","url":null,"abstract":"Proposes a novel integrated scheduling and allocation algorithm suitable for automatic data path synthesis. The algorithm is based on computation of an accurate lower bound on the cost of functional units. The algorithm produces optimal schedules in most cases.<<ETX>>","PeriodicalId":183602,"journal":{"name":"[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125671837","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A novel VLSI solution to a difficult graph problem 一个新的VLSI解决困难的图形问题
[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design Pub Date : 1991-01-04 DOI: 10.1109/ISVD.1991.185104
S. Chakradhar, V. Agrawal
{"title":"A novel VLSI solution to a difficult graph problem","authors":"S. Chakradhar, V. Agrawal","doi":"10.1109/ISVD.1991.185104","DOIUrl":"https://doi.org/10.1109/ISVD.1991.185104","url":null,"abstract":"Presents a VLSI solution of the independent set problem. This graph problem occurs in many applications including computer-aided design. The solution is based on a novel transformation of the graph to a logic circuit. The vertices in the graph are encoded with Boolean variables whose relationships are represented in the logic circuit. The transformation is derived from the energy relation of the neural network model of the logic circuit. Each input vector provides one solution of the independent set problem. The independent set consists of only vertices with true encoding. This new methodology has the potential of solving the problem in real time if programmable logic is used.<<ETX>>","PeriodicalId":183602,"journal":{"name":"[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127448292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A multilayered VLSI array design for multistage interconnection network 多级互连网络的多层VLSI阵列设计
[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design Pub Date : 1991-01-04 DOI: 10.1109/ISVD.1991.185140
R. Mahapatra, B. K. Kar
{"title":"A multilayered VLSI array design for multistage interconnection network","authors":"R. Mahapatra, B. K. Kar","doi":"10.1109/ISVD.1991.185140","DOIUrl":"https://doi.org/10.1109/ISVD.1991.185140","url":null,"abstract":"The multilayered 3D design of an indirect binary N-cube (IBNC) multistage interconnection network (MIN) is presented. The implementation of IBNC MIN in the form of a multilayered array seems to be attractive due to less conventional connections than that in its systolic implementation approach. The area and delay performance is also found to be better compared to other two methods of implementation.<<ETX>>","PeriodicalId":183602,"journal":{"name":"[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126287517","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A new test scheduling algorithm for VLSI systems 一种新的VLSI系统测试调度算法
[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design Pub Date : 1991-01-04 DOI: 10.1109/ISVD.1991.185108
M. Garg, A. Basu, T. C. Wilson, D. Banerji, J. Majithia
{"title":"A new test scheduling algorithm for VLSI systems","authors":"M. Garg, A. Basu, T. C. Wilson, D. Banerji, J. Majithia","doi":"10.1109/ISVD.1991.185108","DOIUrl":"https://doi.org/10.1109/ISVD.1991.185108","url":null,"abstract":"Presents a new test scheduling algorithm based on a new heuristic approach. A new concept of time zone tree has been proposed and the algorithm builds up the tree based on a heuristic cost function. The performance of the algorithm has been compared with existing algorithms and it demonstrates encouraging results.<<ETX>>","PeriodicalId":183602,"journal":{"name":"[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117276856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
New results on channel routing 信道路由的新结果
[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design Pub Date : 1991-01-04 DOI: 10.1109/ISVD.1991.185113
Tai-Tsung Ho, S. Iyengar
{"title":"New results on channel routing","authors":"Tai-Tsung Ho, S. Iyengar","doi":"10.1109/ISVD.1991.185113","DOIUrl":"https://doi.org/10.1109/ISVD.1991.185113","url":null,"abstract":"Presents a new routing concept which guides the selection of wire segments in track-by-track fashion by inspecting the effects of the endpoints of each selected wire segment to column density and vertical constraint graph of the given channel routing problem. This new routing concept has been implemented in the two-layer and three-layer routers. The routing performance of the developed two-layer and three-layer routers has overwhelmingly outperformed all the currently existing two-layer and three-layer routers in most examples in the literature as shown in experimental results.<<ETX>>","PeriodicalId":183602,"journal":{"name":"[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121313812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Fault detection in DCVS circuits DCVS电路中的故障检测
[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design Pub Date : 1991-01-04 DOI: 10.1109/ISVD.1991.185088
B. Vinnakota, N. K. Jha
{"title":"Fault detection in DCVS circuits","authors":"B. Vinnakota, N. K. Jha","doi":"10.1109/ISVD.1991.185088","DOIUrl":"https://doi.org/10.1109/ISVD.1991.185088","url":null,"abstract":"Dynamic CMOS circuits are known to be easier to test, in general, than static CMOS circuits. Differential cascode voltage switch (DCVS) logic belongs to the dynamic CMOS logic family. No comprehensive results on deterministic testing of DCVS circuits have been presented previously. This paper discusses the detection of stuck-open, stuck-on and stuck-at faults in these circuits. A test set which detects all single stuck-on faults in the functional sections of the DCVS gates in the circuit can also be guaranteed to detect all multiple stuck-on, multiple stuck-open and unidirectional stuck-at faults in these sections, even when the faults are not confined to the functional section of a single gate. All detectable faults in the precharge, access and buffer transistors are also detected by the test set.<<ETX>>","PeriodicalId":183602,"journal":{"name":"[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design","volume":"2016 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128443095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Yield and layout issues in fault tolerant VLSI architectures 容错VLSI架构中的良率与布局问题
[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design Pub Date : 1991-01-04 DOI: 10.1109/ISVD.1991.185126
S. Upadhyaya, Yung-Yuan Chen
{"title":"Yield and layout issues in fault tolerant VLSI architectures","authors":"S. Upadhyaya, Yung-Yuan Chen","doi":"10.1109/ISVD.1991.185126","DOIUrl":"https://doi.org/10.1109/ISVD.1991.185126","url":null,"abstract":"Yield and layout are two important but often ignored issues in the design of fault tolerant VLSI systems. The authors present a framework for the systematic analysis of yield and area-efficient layout of fault-tolerant architectures. A multiple level redundancy tree is considered as a target architecture to demonstrate their analysis technique.<<ETX>>","PeriodicalId":183602,"journal":{"name":"[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126891648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Design for testability and test generation with two clocks 设计可测试性和测试生成与两个时钟
[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design Pub Date : 1991-01-04 DOI: 10.1109/ISVD.1991.185102
V. Agrawal, S. Seth, J. Deogun
{"title":"Design for testability and test generation with two clocks","authors":"V. Agrawal, S. Seth, J. Deogun","doi":"10.1109/ISVD.1991.185102","DOIUrl":"https://doi.org/10.1109/ISVD.1991.185102","url":null,"abstract":"Proposes a novel design for testability method that enhances the controllability of storage elements by use of additional clock lines. The scheme is applicable to synchronous circuits but is otherwise transparent to the designer. The associated area and speed penalties are minimal compared to scan based methods. However, a sequential ATPG system is necessary for test generation. The basic idea is to use independent clock lines to control disjoint groups of flip-flops. No cyclic path is permitted among the flip-flops of the same group. During testing, a selected group can be made to hold its state by disabling its clock lines. In the normal mode, all clock lines carry the same system clock signal. With the appropriate partitioning of flip-flops, the length of the vector sequence produced by the test generator for a fault is drastically reduced. An n-stage binary counter is used for experimental verification of reduction in test length by the proposed technique.<<ETX>>","PeriodicalId":183602,"journal":{"name":"[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121572489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Using high-level primitives to speed up circuit partitioning in a mixed scan and non-scan environment for system level test generation 在系统级测试生成的混合扫描和非扫描环境中，使用高级原语加速电路划分
[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design Pub Date : 1991-01-04 DOI: 10.1109/ISVD.1991.185103
S. Kode
{"title":"Using high-level primitives to speed up circuit partitioning in a mixed scan and non-scan environment for system level test generation","authors":"S. Kode","doi":"10.1109/ISVD.1991.185103","DOIUrl":"https://doi.org/10.1109/ISVD.1991.185103","url":null,"abstract":"An approach to carving circuit partitions starting and stopping at controllable and observable points using high-level primitives is described. This approach allows considerable speed up over gate level partitioning. The minimum set of properties to accommodate multi-input, multi-output primitives is presented. The approach is both memory efficient and fast allowing for both deterministic and interactive heuristic partitioning at the system level. Partitioning is orthogonal to test generation, and the best scan test generator can still be used on the generated scan targets. Practical application of the approach for the system level scan test generation of the Apollo DN10000 and its CPU upgrade, both designs of more than a million gates, are presented. Evolution of the techniques to accommodate new technology will be addressed. Partitioning for test generation for both stuck-at and delay faults are addressed.<<ETX>>","PeriodicalId":183602,"journal":{"name":"[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123229040","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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