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[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design最新文献

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Defect and design error location procedure-theoretical basis 缺陷和设计错误定位程序-理论基础
[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design Pub Date : 1991-01-04 DOI: 10.1109/ISVD.1991.185124
Wojciech Maly
{"title":"Defect and design error location procedure-theoretical basis","authors":"Wojciech Maly","doi":"10.1109/ISVD.1991.185124","DOIUrl":"https://doi.org/10.1109/ISVD.1991.185124","url":null,"abstract":"In this paper theoretical basis for VLSI chip defect diagnosis and defect location are discussed and a simple diagnosability measure is introduced. The proposed framework can be used to evaluate quality of defect diagnosis oriented testing vectors, as well as, for the development of test generation algorithms.<<ETX>>","PeriodicalId":183602,"journal":{"name":"[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125223696","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
HVH. . .VH multi-layer channel routing vh . . vh多层通道路由
[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design Pub Date : 1991-01-04 DOI: 10.1109/ISVD.1991.185130
Jee-Soo Lee, Yookun Cho
{"title":"HVH. . .VH multi-layer channel routing","authors":"Jee-Soo Lee, Yookun Cho","doi":"10.1109/ISVD.1991.185130","DOIUrl":"https://doi.org/10.1109/ISVD.1991.185130","url":null,"abstract":"The authors present an algorithm for the HVH. . .VH multi-layer channel routing problem. First they determine the net groups to be positioned on the same track using a left-edge algorithm. The vertical constraint graph made from these net groups may contain many cycles. There is an attempt to remove the cycles through proper layer assignment and maze routing.<<ETX>>","PeriodicalId":183602,"journal":{"name":"[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134054449","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A novel electrical test structure for measuring misalignment between polysilicon and active area in MOS VLSI technologies 一种用于测量MOS VLSI技术中多晶硅与有源区不对准的新型电测试结构
[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design Pub Date : 1991-01-04 DOI: 10.1109/ISVD.1991.185138
S. Srivastava, A. Kansal, C. Shekhar
{"title":"A novel electrical test structure for measuring misalignment between polysilicon and active area in MOS VLSI technologies","authors":"S. Srivastava, A. Kansal, C. Shekhar","doi":"10.1109/ISVD.1991.185138","DOIUrl":"https://doi.org/10.1109/ISVD.1991.185138","url":null,"abstract":"A novel test structure has been designed to electrically measure the misalignment between polysilicon and the active area in MOS technologies. This alignment is one of the most critical alignments in small geometry integrated circuit processing. The structure exploits the channel width change of specially designed MOS transistors resulting from the misalignment between the active area and polysilicon layers to develop a proportionate differential current sensing arrangement. A calibrating structure is used to translate the measured differential current to actual microns.<<ETX>>","PeriodicalId":183602,"journal":{"name":"[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115782128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Fault modeling and testable design of 2-level complex ECL gates 2级复杂ECL门的故障建模与可测试性设计
[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design Pub Date : 1991-01-04 DOI: 10.1109/ISVD.1991.185087
S. Menon, Y. Malaiya, A. Jayasumana
{"title":"Fault modeling and testable design of 2-level complex ECL gates","authors":"S. Menon, Y. Malaiya, A. Jayasumana","doi":"10.1109/ISVD.1991.185087","DOIUrl":"https://doi.org/10.1109/ISVD.1991.185087","url":null,"abstract":"Bipolar emitter coupled logic (ECL) devices can now be fabricated at very high densities and much lower power consumption. Behaviour of 2-level complex ECL gates is examined in the presence of physical faults. It is shown that the conventional stuck-at fault model cannot represent a majority of circuit level faults. A new augmented stuck-at fault model is presented which provides a significantly higher coverage of physical failures. A testable design approach is presented for on-line detection of certain error conditions occurring in gates with true and complementary outputs which is a normal implementation for ECL devices.<<ETX>>","PeriodicalId":183602,"journal":{"name":"[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114123211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Elements of a design framework for module generators design and usage 设计框架中的元素用于模块生成器的设计和使用
[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design Pub Date : 1991-01-04 DOI: 10.1109/ISVD.1991.185098
W. Sakowski
{"title":"Elements of a design framework for module generators design and usage","authors":"W. Sakowski","doi":"10.1109/ISVD.1991.185098","DOIUrl":"https://doi.org/10.1109/ISVD.1991.185098","url":null,"abstract":"Presents a procedural layout description language ALL and elements of design environment that supports it. Language capabilities in defining module generators are shown. Ways of integrating textual and graphical layout representations are presented. A proposal of language implementation based on object-oriented paradigm is discussed.<<ETX>>","PeriodicalId":183602,"journal":{"name":"[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114909479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Synthesis of multiple outputs CMOS gates 多输出CMOS门的合成
[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design Pub Date : 1991-01-04 DOI: 10.1109/ISVD.1991.185092
G. Buonanno, D. Sciuto, R. Stefanelli
{"title":"Synthesis of multiple outputs CMOS gates","authors":"G. Buonanno, D. Sciuto, R. Stefanelli","doi":"10.1109/ISVD.1991.185092","DOIUrl":"https://doi.org/10.1109/ISVD.1991.185092","url":null,"abstract":"Design of static CMOS gates for multiple output functions is presented. Two techniques for minimization of multiple output functions at the switching level are introduced. These techniques are based on innovative transistor interconnection structures named delta and lambda networks. Design examples on double output functions are provided. It is shown that the two techniques can be combined together, if necessary, to obtain further area reductions.<<ETX>>","PeriodicalId":183602,"journal":{"name":"[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121829885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design of high-speed VLSI circuits for mainframe computers 大型计算机高速VLSI电路的设计
[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design Pub Date : 1991-01-04 DOI: 10.1109/ISVD.1991.185118
S. Seinecke
{"title":"Design of high-speed VLSI circuits for mainframe computers","authors":"S. Seinecke","doi":"10.1109/ISVD.1991.185118","DOIUrl":"https://doi.org/10.1109/ISVD.1991.185118","url":null,"abstract":"The next generation of mainframe computers will use fast BiCMOS ASICS having upto 100000 gate functions. Static CMOS RAMs with 3 ns access time will be embedded in bipolar ECL logic circuits with 50 ps gate delay. Standard cells will be intensively applied in order to obtain very fast macros with reduced power and space. Delay rules have to be designed in order to predict net delay and delay tolerances; line delay will dominate. The CAD system has to offer tools for optimum design of critical paths. TAB packages are the best choice.<<ETX>>","PeriodicalId":183602,"journal":{"name":"[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125599517","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A scan-based BIST technique using pair-wise compare of identical components 一种基于扫描的BIST技术，使用相同组件的成对比较
[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design Pub Date : 1991-01-04 DOI: 10.1109/ISVD.1991.185121
B. Nadeau-Dostie, P. Wilcox, V. Agarwal
{"title":"A scan-based BIST technique using pair-wise compare of identical components","authors":"B. Nadeau-Dostie, P. Wilcox, V. Agarwal","doi":"10.1109/ISVD.1991.185121","DOIUrl":"https://doi.org/10.1109/ISVD.1991.185121","url":null,"abstract":"Addresses the problem of efficiently testing scannable ASICs in a board-level and system-level environment. The method makes use of a serial testability bus (ETM or IEEE 1149.1) and takes advantage of the presence of identical components on the boards. The main benefits of the method are a significant reduction in test time and test data to be stored. Results obtained for an actual system show a reduction in test time of about 20 times for a module with 50 ASICs. The extra board area required was less than 2% for all boards of the module.<<ETX>>","PeriodicalId":183602,"journal":{"name":"[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127785250","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
A class of hierarchical networks for VLSI/WSI based multicomputers 一类基于VLSI/WSI的多计算机分层网络
[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design Pub Date : 1991-01-04 DOI: 10.1109/ISVD.1991.185128
Chienhua Chen, D. Agrawal, J. R. Burke
{"title":"A class of hierarchical networks for VLSI/WSI based multicomputers","authors":"Chienhua Chen, D. Agrawal, J. R. Burke","doi":"10.1109/ISVD.1991.185128","DOIUrl":"https://doi.org/10.1109/ISVD.1991.185128","url":null,"abstract":"A class of hierarchical networks is proposed for multicomputer implementation using VLSI and wafer scale integration (VLSI/WSI). These networks, called DBCube, connect clusters of cube topology based nodes with a De Bruijn graph. The nodes are identical and can be easily extended to a larger size. The cube topology for local communication allows easy embedding of parallel algorithms and the De Bruijn graph provides shortest distance among different clusters. The authors compare the DBCube with other networks in terms of topological properties. They compute the silicon area requirement of DBCube. The DBCube topology is such that testing of the network before metallization make it easily configurable to DBCube of smaller size. Potential extension of the DBCube is also addressed.<<ETX>>","PeriodicalId":183602,"journal":{"name":"[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133471768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Modified interval line representation and its applications to planar routing problems 改进区间线表示法及其在平面布线问题中的应用
[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design Pub Date : 1991-01-04 DOI: 10.1109/ISVD.1991.185112
S. Saxena, V. C. Prasad, P. Bhatt
{"title":"Modified interval line representation and its applications to planar routing problems","authors":"S. Saxena, V. C. Prasad, P. Bhatt","doi":"10.1109/ISVD.1991.185112","DOIUrl":"https://doi.org/10.1109/ISVD.1991.185112","url":null,"abstract":"A modified interval line representation is proposed. This representation makes it possible to speed up some heuristics and algorithms for planar routing problems. This technique is illustrated by speeding up the heuristic proposed by Tsukiyama and Kuh for the double row routing problem. The heuristic suggested by Tsukiyama and Kuh for double row routing problem, can be implemented in O(n/sup 2/rlg r) time algorithm, whereas the implementation suggested by Tsukiyama and Kuh requires O(n/sup 3/r) time. It is also shown that the heuristic can be implemented in parallel in O(lg/sup 2/n+lg r) time using O(N/sup 4/+n/sup 2/r) processors on the concurrent read exclusive write (CREW) model.<<ETX>>","PeriodicalId":183602,"journal":{"name":"[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design","volume":"152 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131759427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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