一种基于扫描的BIST技术，使用相同组件的成对比较

[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design Pub Date : 1991-01-04 DOI:10.1109/ISVD.1991.185121

B. Nadeau-Dostie, P. Wilcox, V. Agarwal

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引用次数: 18

摘要

解决了在板级和系统级环境中有效测试可扫描asic的问题。该方法利用串行可测试性总线(ETM或IEEE 1149.1)，并利用电路板上相同组件的存在。该方法的主要优点是显著减少了测试时间和需要存储的测试数据。在实际系统中获得的结果表明，对于包含50个asic的模块，测试时间减少了约20倍。该模块所有板所需的额外板面积小于2%。

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A scan-based BIST technique using pair-wise compare of identical components

Addresses the problem of efficiently testing scannable ASICs in a board-level and system-level environment. The method makes use of a serial testability bus (ETM or IEEE 1149.1) and takes advantage of the presence of identical components on the boards. The main benefits of the method are a significant reduction in test time and test data to be stored. Results obtained for an actual system show a reduction in test time of about 20 times for a module with 50 ASICs. The extra board area required was less than 2% for all boards of the module.<>

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来源期刊

[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design

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