Design of high-speed VLSI circuits for mainframe computers

Abstract

The next generation of mainframe computers will use fast BiCMOS ASICS having upto 100000 gate functions. Static CMOS RAMs with 3 ns access time will be embedded in bipolar ECL logic circuits with 50 ps gate delay. Standard cells will be intensively applied in order to obtain very fast macros with reduced power and space. Delay rules have to be designed in order to predict net delay and delay tolerances; line delay will dominate. The CAD system has to offer tools for optimum design of critical paths. TAB packages are the best choice.<>