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[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design最新文献

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An overlap model for routing 路由的重叠模型
[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design Pub Date : 1991-01-04 DOI: 10.1109/ISVD.1991.185111
K. Chaudhary, P. Robinson
{"title":"An overlap model for routing","authors":"K. Chaudhary, P. Robinson","doi":"10.1109/ISVD.1991.185111","DOIUrl":"https://doi.org/10.1109/ISVD.1991.185111","url":null,"abstract":"Describes a new approach to routing in two layers using the overlap model of layer assignment. The overlap model allows tracks to be laid on top of each other as permitted by the real design rules. The technique is very simple and elegant with results more compact than the optimal solutions under the directional model and with at most one via per subnet. It is illustrated here in the context of over-the-cell channel routing.<<ETX>>","PeriodicalId":183602,"journal":{"name":"[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design","volume":"100 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114089284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Parallel test pattern generation using Boolean satisfiability 使用布尔可满足性的并行测试模式生成
[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design Pub Date : 1991-01-04 DOI: 10.1109/ISVD.1991.185095
V. Sivaramakrishnan, S. Seth, P. Agrawal
{"title":"Parallel test pattern generation using Boolean satisfiability","authors":"V. Sivaramakrishnan, S. Seth, P. Agrawal","doi":"10.1109/ISVD.1991.185095","DOIUrl":"https://doi.org/10.1109/ISVD.1991.185095","url":null,"abstract":"Recently, Larrabee proposed a sequential test generation algorithm for combinational circuits based on Boolean satisfiability and presented results on benchmark circuits in support of the viability of this approach. Parallel implementations of test generation algorithms are attractive in view of the known difficulty (NP-completeness) of the problem. This paper suggests parallel versions of Larrabee's algorithm, suitable for implementation on shared-memory and message-passing multicomputers.<<ETX>>","PeriodicalId":183602,"journal":{"name":"[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115334269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
An algorithm for minimising the number of test cycles 最小化测试周期数的算法
[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design Pub Date : 1991-01-04 DOI: 10.1109/ISVD.1991.185109
A. Diwan
{"title":"An algorithm for minimising the number of test cycles","authors":"A. Diwan","doi":"10.1109/ISVD.1991.185109","DOIUrl":"https://doi.org/10.1109/ISVD.1991.185109","url":null,"abstract":"The scan-path method for testing a VLSI circuit uses a shift register to store the test vectors, and a sequence of test patterns is applied by shifting in new patterns one bit at a time. This paper presents an algorithm to find the order in which the test patterns should be applied in order to minimise the number of shift operations required. The algorithm can be shown to be optimal under certain conditions.<<ETX>>","PeriodicalId":183602,"journal":{"name":"[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116312939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Development of ASIC datapath compilers for gate array designs 用于门阵列设计的ASIC数据路径编译器的开发
[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design Pub Date : 1991-01-04 DOI: 10.1109/ISVD.1991.185133
B. Mitra, K. Rao, S. Jha, J. Bagherli
{"title":"Development of ASIC datapath compilers for gate array designs","authors":"B. Mitra, K. Rao, S. Jha, J. Bagherli","doi":"10.1109/ISVD.1991.185133","DOIUrl":"https://doi.org/10.1109/ISVD.1991.185133","url":null,"abstract":"The authors present a complete development flow of ASIC datapath compilers for gate array designs. The module design and usage flow for the parameterized datapath elements is described. The efficiency achieved through the use of a highly integrated design environment is highlighted.<<ETX>>","PeriodicalId":183602,"journal":{"name":"[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123405592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A VLSI routing framework for use on a multiprocessor workstation 用于多处理器工作站的VLSI路由框架
[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design Pub Date : 1991-01-04 DOI: 10.1109/ISVD.1991.185097
V. Sagar, R. Massara
{"title":"A VLSI routing framework for use on a multiprocessor workstation","authors":"V. Sagar, R. Massara","doi":"10.1109/ISVD.1991.185097","DOIUrl":"https://doi.org/10.1109/ISVD.1991.185097","url":null,"abstract":"With the coming of age of CAD workstations based on parallel hardware and the increasing need to accelerate CAD tools, there is a demand to exploit parallelism on general-purpose parallel hardware to achieve speedup. Hence, a novel VLSI routing framework was investigated for a parallel CAD workstation.<<ETX>>","PeriodicalId":183602,"journal":{"name":"[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129079974","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
State machine design-an interactive approach 状态机设计——一种交互式方法
[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design Pub Date : 1991-01-04 DOI: 10.1109/ISVD.1991.185090
J. Bastian, A. Savargaonkar, S. Venkateswaren, K. Rao, T. Nagesh, K.S. Raghunthan
{"title":"State machine design-an interactive approach","authors":"J. Bastian, A. Savargaonkar, S. Venkateswaren, K. Rao, T. Nagesh, K.S. Raghunthan","doi":"10.1109/ISVD.1991.185090","DOIUrl":"https://doi.org/10.1109/ISVD.1991.185090","url":null,"abstract":"Finite state machines are essential components in digital systems. This paper describes a tool for designing a finite state machine from its behavioral description. Useful user interfaces for describing a state machine and for verification of its behavior are the important contributions made in this paper.<<ETX>>","PeriodicalId":183602,"journal":{"name":"[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124010134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Simulated annealing-based channel routing on hypercube computers 在超立方体计算机上模拟基于退火的信道路由
[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design Pub Date : 1991-01-04 DOI: 10.1109/ISVD.1991.185096
R. Mall, L. Patnaik, S. Raman
{"title":"Simulated annealing-based channel routing on hypercube computers","authors":"R. Mall, L. Patnaik, S. Raman","doi":"10.1109/ISVD.1991.185096","DOIUrl":"https://doi.org/10.1109/ISVD.1991.185096","url":null,"abstract":"Many times, routing of signal nets in the layout design of VLSI circuits turns out to be a bottleneck in designing complex chips, due to the inherent compute-intensive nature of this task. Parallel processing of the routing problem holds promise for mitigating this situation. The authors present a parallel channel routing algorithm that is targetted to run on loosely coupled computers like hypercubes. The proposed parallel algorithm employs simulated annealing technique for achieving near-optimum solutions. For efficient execution, attempts have been made to reduce the communication overheads by restricting broadcast of updates only to cases of interprocessor net transfers. Performance evaluation studies on the algorithm show promising results.<<ETX>>","PeriodicalId":183602,"journal":{"name":"[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design","volume":"601 1-3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122618930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A new processor interconnection structure for fault tolerant processor arrays 一种容错处理器阵列的新型处理器互连结构
[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design Pub Date : 1991-01-04 DOI: 10.1109/ISVD.1991.185127
H. Youn, A. Singh
{"title":"A new processor interconnection structure for fault tolerant processor arrays","authors":"H. Youn, A. Singh","doi":"10.1109/ISVD.1991.185127","DOIUrl":"https://doi.org/10.1109/ISVD.1991.185127","url":null,"abstract":"Processor arrays integrated on a wafer can display a high performance mainly due to the short communication delay between processors. However, an efficient fault tolerance scheme is essential to yield the desired array because some components on wafer can be defective. In this paper, the authors present a new processor interconnection structure which requires much less chip area than the traditional design for restructuring a rectangular array. Because interconnection of a fault tolerant processor array occupies a substantial chip area, especially for large word parallel systems, this will significantly improve the overall performance of the processor arrays in VLSI/WSI.<<ETX>>","PeriodicalId":183602,"journal":{"name":"[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116180065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Efficient testing techniques for bit and digit-serial arrays 位和数字串行阵列的有效测试技术
[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design Pub Date : 1991-01-04 DOI: 10.1109/ISVD.1991.185107
A. Chatterjee, R. Roy, J. Abraham, J. Patel
{"title":"Efficient testing techniques for bit and digit-serial arrays","authors":"A. Chatterjee, R. Roy, J. Abraham, J. Patel","doi":"10.1109/ISVD.1991.185107","DOIUrl":"https://doi.org/10.1109/ISVD.1991.185107","url":null,"abstract":"Bit and digit-serial architectures are used extensively in digital signal processing applications. Testing these structures is a very difficult problem due to low controllability/observability and complex interconnections between the circuit components. Efficient test generation techniques have been developed and applied to three classes of bit and digit-serial circuits. The testing techniques are novel and address issues such as embedded finite state machine testing, pipelining of test vectors, time to space transformation of iterative systems, and testing of cascaded cells. Test complexity issues are also discussed.<<ETX>>","PeriodicalId":183602,"journal":{"name":"[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129673138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Additive cellular automata (CA) as a primitive structure for signature analysis 加性元胞自动机(CA)是一种用于特征分析的原始结构
[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design Pub Date : 1991-01-04 DOI: 10.1109/ISVD.1991.185123
S. Misra, P. Chaudhuri
{"title":"Additive cellular automata (CA) as a primitive structure for signature analysis","authors":"S. Misra, P. Chaudhuri","doi":"10.1109/ISVD.1991.185123","DOIUrl":"https://doi.org/10.1109/ISVD.1991.185123","url":null,"abstract":"Additive cellular automata (CA) have been proposed as an alternative to LFSR for signature analysis. It has also been shown that for nongroup CAs the steady state aliasing error probability (AEP) can be less than 2/sup -n/ (for an n-cell CA). A closed form expression for the steady state AEP for a special class of CA has been derived. From the closed form expression it has been shown that the steady state AEP is less than 2/sup -n/ for some values of p (error probability) and n. A procedure has been outlined to synthesise a CA over any length of the above class.<<ETX>>","PeriodicalId":183602,"journal":{"name":"[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122029539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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