Efficient testing techniques for bit and digit-serial arrays

Abstract

Bit and digit-serial architectures are used extensively in digital signal processing applications. Testing these structures is a very difficult problem due to low controllability/observability and complex interconnections between the circuit components. Efficient test generation techniques have been developed and applied to three classes of bit and digit-serial circuits. The testing techniques are novel and address issues such as embedded finite state machine testing, pipelining of test vectors, time to space transformation of iterative systems, and testing of cascaded cells. Test complexity issues are also discussed.<>