A novel electrical test structure for measuring misalignment between polysilicon and active area in MOS VLSI technologies

A novel test structure has been designed to electrically measure the misalignment between polysilicon and the active area in MOS technologies. This alignment is one of the most critical alignments in small geometry integrated circuit processing. The structure exploits the channel width change of specially designed MOS transistors resulting from the misalignment between the active area and polysilicon layers to develop a proportionate differential current sensing arrangement. A calibrating structure is used to translate the measured differential current to actual microns.<>