大型计算机高速VLSI电路的设计

[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design Pub Date : 1991-01-04 DOI:10.1109/ISVD.1991.185118

S. Seinecke

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引用次数: 0

摘要

下一代大型计算机将使用具有多达100000门功能的快速BiCMOS ASICS。具有3ns访问时间的静态CMOS ram将嵌入具有50ps门延迟的双极ECL逻辑电路中。标准单元将被广泛应用，以便在减少功率和空间的情况下获得非常快的宏。为了预测净延迟和延迟容限，必须设计延迟规则;线路延迟将占主导地位。CAD系统必须为关键路径的优化设计提供工具。TAB包是最好的选择。

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Design of high-speed VLSI circuits for mainframe computers

The next generation of mainframe computers will use fast BiCMOS ASICS having upto 100000 gate functions. Static CMOS RAMs with 3 ns access time will be embedded in bipolar ECL logic circuits with 50 ps gate delay. Standard cells will be intensively applied in order to obtain very fast macros with reduced power and space. Delay rules have to be designed in order to predict net delay and delay tolerances; line delay will dominate. The CAD system has to offer tools for optimum design of critical paths. TAB packages are the best choice.<>

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[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design

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