多级互连网络的多层VLSI阵列设计

[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design Pub Date : 1991-01-04 DOI:10.1109/ISVD.1991.185140

R. Mahapatra, B. K. Kar

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引用次数: 0

摘要

提出了一种间接二进制n -立方体(IBNC)多级互连网络(MIN)的多层三维设计方法。以多层阵列的形式实现IBNC MIN似乎更有吸引力，因为它的传统连接比收缩实现方法少。与其他两种实现方法相比，该方法的面积和延迟性能也更好

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A multilayered VLSI array design for multistage interconnection network

The multilayered 3D design of an indirect binary N-cube (IBNC) multistage interconnection network (MIN) is presented. The implementation of IBNC MIN in the form of a multilayered array seems to be attractive due to less conventional connections than that in its systolic implementation approach. The area and delay performance is also found to be better compared to other two methods of implementation.<>

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[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design

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