容错VLSI架构中的良率与布局问题

[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design Pub Date : 1991-01-04 DOI:10.1109/ISVD.1991.185126

S. Upadhyaya, Yung-Yuan Chen

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引用次数: 4

摘要

在超大规模集成电路系统的容错设计中，良率和布局是两个重要但经常被忽略的问题。作者提出了一个框架，用于系统分析容错架构的成品率和面积效率布局。一个多层次的冗余树被认为是一个目标体系结构来演示他们的分析技术。

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Yield and layout issues in fault tolerant VLSI architectures

Yield and layout are two important but often ignored issues in the design of fault tolerant VLSI systems. The authors present a framework for the systematic analysis of yield and area-efficient layout of fault-tolerant architectures. A multiple level redundancy tree is considered as a target architecture to demonstrate their analysis technique.<>

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[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design

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