A multilayered VLSI array design for multistage interconnection network

Abstract

The multilayered 3D design of an indirect binary N-cube (IBNC) multistage interconnection network (MIN) is presented. The implementation of IBNC MIN in the form of a multilayered array seems to be attractive due to less conventional connections than that in its systolic implementation approach. The area and delay performance is also found to be better compared to other two methods of implementation.<>