Using high-level primitives to speed up circuit partitioning in a mixed scan and non-scan environment for system level test generation

Abstract

An approach to carving circuit partitions starting and stopping at controllable and observable points using high-level primitives is described. This approach allows considerable speed up over gate level partitioning. The minimum set of properties to accommodate multi-input, multi-output primitives is presented. The approach is both memory efficient and fast allowing for both deterministic and interactive heuristic partitioning at the system level. Partitioning is orthogonal to test generation, and the best scan test generator can still be used on the generated scan targets. Practical application of the approach for the system level scan test generation of the Apollo DN10000 and its CPU upgrade, both designs of more than a million gates, are presented. Evolution of the techniques to accommodate new technology will be addressed. Partitioning for test generation for both stuck-at and delay faults are addressed.<>