{"title":"线性泄漏RC网格/树的信号延迟","authors":"N. K. Jain, V. Prasad, A. Bhattacharyya","doi":"10.1109/ISVD.1991.185116","DOIUrl":null,"url":null,"abstract":"As chip dimensions are reduced, the performance of integrated circuits is limited by the delays associated with the interconnections. For the purpose of propagation delay estimation in digital circuits, these interconnections can be modelled by leaky RC tree/line/mesh. Signal delay in a nonleaky RC tree can be estimated by a tree algorithm. In this paper a modified tree algorithm (linear order) is presented for estimating signal delay in a leaky RC tree with nonzero initial conditions.<<ETX>>","PeriodicalId":183602,"journal":{"name":"[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design","volume":"418 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Signal delay in linear leaky RC mesh/tree\",\"authors\":\"N. K. Jain, V. Prasad, A. Bhattacharyya\",\"doi\":\"10.1109/ISVD.1991.185116\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"As chip dimensions are reduced, the performance of integrated circuits is limited by the delays associated with the interconnections. For the purpose of propagation delay estimation in digital circuits, these interconnections can be modelled by leaky RC tree/line/mesh. Signal delay in a nonleaky RC tree can be estimated by a tree algorithm. In this paper a modified tree algorithm (linear order) is presented for estimating signal delay in a leaky RC tree with nonzero initial conditions.<<ETX>>\",\"PeriodicalId\":183602,\"journal\":{\"name\":\"[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design\",\"volume\":\"418 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1991-01-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISVD.1991.185116\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISVD.1991.185116","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
As chip dimensions are reduced, the performance of integrated circuits is limited by the delays associated with the interconnections. For the purpose of propagation delay estimation in digital circuits, these interconnections can be modelled by leaky RC tree/line/mesh. Signal delay in a nonleaky RC tree can be estimated by a tree algorithm. In this paper a modified tree algorithm (linear order) is presented for estimating signal delay in a leaky RC tree with nonzero initial conditions.<>