一种基于LZ的数据压缩收缩芯片

N. Ranganathan, S. Henriques
{"title":"一种基于LZ的数据压缩收缩芯片","authors":"N. Ranganathan, S. Henriques","doi":"10.1109/ISVD.1991.185144","DOIUrl":null,"url":null,"abstract":"The authors describe the design of a systolic VLSI chip which implements the LZ technique for data compression. The LZ-based compression method due to Lempel and Ziv (1977) is a very powerful technique and gives very high compression efficiency for text as well as image data. The architecture is systolic and uses the principles of pipelining and parallelism in order to obtain high speed and throughput. The order of complexity of the computations is reduced from n/sup 2/ to n. The chip can be integrated into real time systems so that data can be compressed and decompressed on-the-fly. A prototype CMOS compression chip implementing a systolic array of 9 processors has been designed and verified and currently, is being fabricated. The chip is expected to operate at 20 MHz and yield a compression rate of about 20 million characters per second.<<ETX>>","PeriodicalId":183602,"journal":{"name":"[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design","volume":"18 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"A systolic chip for LZ based data compression\",\"authors\":\"N. Ranganathan, S. Henriques\",\"doi\":\"10.1109/ISVD.1991.185144\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The authors describe the design of a systolic VLSI chip which implements the LZ technique for data compression. The LZ-based compression method due to Lempel and Ziv (1977) is a very powerful technique and gives very high compression efficiency for text as well as image data. The architecture is systolic and uses the principles of pipelining and parallelism in order to obtain high speed and throughput. The order of complexity of the computations is reduced from n/sup 2/ to n. The chip can be integrated into real time systems so that data can be compressed and decompressed on-the-fly. A prototype CMOS compression chip implementing a systolic array of 9 processors has been designed and verified and currently, is being fabricated. The chip is expected to operate at 20 MHz and yield a compression rate of about 20 million characters per second.<<ETX>>\",\"PeriodicalId\":183602,\"journal\":{\"name\":\"[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design\",\"volume\":\"18 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1991-01-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISVD.1991.185144\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISVD.1991.185144","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3

摘要

介绍了一种采用LZ技术进行数据压缩的收缩式VLSI芯片的设计。Lempel和Ziv(1977)提出的基于lz的压缩方法是一种非常强大的技术,可以对文本和图像数据进行非常高的压缩效率。该体系结构是收缩的,并使用流水线和并行的原则,以获得高速度和吞吐量。计算复杂度从n/sup 2/降至n。该芯片可以集成到实时系统中,从而可以实时压缩和解压缩数据。一个原型CMOS压缩芯片实现了9个处理器的收缩阵列已经设计和验证,目前正在制造。该芯片的工作频率预计为20mhz,压缩率约为每秒2000万个字符。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A systolic chip for LZ based data compression
The authors describe the design of a systolic VLSI chip which implements the LZ technique for data compression. The LZ-based compression method due to Lempel and Ziv (1977) is a very powerful technique and gives very high compression efficiency for text as well as image data. The architecture is systolic and uses the principles of pipelining and parallelism in order to obtain high speed and throughput. The order of complexity of the computations is reduced from n/sup 2/ to n. The chip can be integrated into real time systems so that data can be compressed and decompressed on-the-fly. A prototype CMOS compression chip implementing a systolic array of 9 processors has been designed and verified and currently, is being fabricated. The chip is expected to operate at 20 MHz and yield a compression rate of about 20 million characters per second.<>
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