{"title":"自动数据路径合成,避免全局互连","authors":"V. K. Raj, C.S. Patwardhan","doi":"10.1109/ISVD.1991.185085","DOIUrl":null,"url":null,"abstract":"Incorporates into a behavioral synthesis system an algorithm to minimize global interconnects in the data path. In order to accomplish this, the authors define a model of the data path to almost completely avoid global interconnects. In this approach, they pay the penalty of extra registers and extra microinstructions to avoid global interconnects. The proposed model of the data path results in large area savings in behavioral synthesis.<<ETX>>","PeriodicalId":183602,"journal":{"name":"[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design","volume":"46 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Automated data path synthesis to avoid global interconnects\",\"authors\":\"V. K. Raj, C.S. Patwardhan\",\"doi\":\"10.1109/ISVD.1991.185085\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Incorporates into a behavioral synthesis system an algorithm to minimize global interconnects in the data path. In order to accomplish this, the authors define a model of the data path to almost completely avoid global interconnects. In this approach, they pay the penalty of extra registers and extra microinstructions to avoid global interconnects. The proposed model of the data path results in large area savings in behavioral synthesis.<<ETX>>\",\"PeriodicalId\":183602,\"journal\":{\"name\":\"[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design\",\"volume\":\"46 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1991-01-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISVD.1991.185085\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISVD.1991.185085","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Automated data path synthesis to avoid global interconnects
Incorporates into a behavioral synthesis system an algorithm to minimize global interconnects in the data path. In order to accomplish this, the authors define a model of the data path to almost completely avoid global interconnects. In this approach, they pay the penalty of extra registers and extra microinstructions to avoid global interconnects. The proposed model of the data path results in large area savings in behavioral synthesis.<>