A systolic chip for LZ based data compression

Abstract

The authors describe the design of a systolic VLSI chip which implements the LZ technique for data compression. The LZ-based compression method due to Lempel and Ziv (1977) is a very powerful technique and gives very high compression efficiency for text as well as image data. The architecture is systolic and uses the principles of pipelining and parallelism in order to obtain high speed and throughput. The order of complexity of the computations is reduced from n/sup 2/ to n. The chip can be integrated into real time systems so that data can be compressed and decompressed on-the-fly. A prototype CMOS compression chip implementing a systolic array of 9 processors has been designed and verified and currently, is being fabricated. The chip is expected to operate at 20 MHz and yield a compression rate of about 20 million characters per second.<>