On reducing test length in LFSR based testing

Abstract

Proposes a new method for generating test patterns in the BIT (built-in testing) environment. This method reduces the testing time under both deterministic and pseudo-random testing, for a desired fault coverage. It relies on the fact that the LFSR (linear feedback shift register) sequence is deterministic. Since the position of any test vector in this sequence can be predicted, the starting vectors (seeds) can be rightly chosen and thereby obtain maximal number of test vectors in minimal time. However, even for reasonably long LFSRs, the length of the sequence can be exorbitantly large, rendering it impractical to search the whole length. The authors propose a technique to overcome this problem, and predict the position of a test vector in the LFSR sequence, in a computationally feasible manner.<>