A switched capacitor filter synthesis system with built-in design for manufacturability

M. Mehendale
{"title":"A switched capacitor filter synthesis system with built-in design for manufacturability","authors":"M. Mehendale","doi":"10.1109/ISVD.1991.185106","DOIUrl":null,"url":null,"abstract":"The paper presents a switched capacitor filter synthesis system with yield estimation and optimization as the integral components of the design environment. The design process is an iterative process involving filter synthesis and yield estimation. Different design choices such as filter order, approximation, circuit topology, etc., affect the yield and also other parameters such as filter area, noise and dynamic range. The integrated environment offers effective mechanisms for exploring the design decision space to achieve the optimum in terms of yield and other design considerations. The paper describes the filter synthesis, yield estimation and optimization aspects of the system. The capabilities offered in the areas of data and flow management are also discussed. The results for a low pass filter design are presented.<<ETX>>","PeriodicalId":183602,"journal":{"name":"[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design","volume":"44 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISVD.1991.185106","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
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Abstract

The paper presents a switched capacitor filter synthesis system with yield estimation and optimization as the integral components of the design environment. The design process is an iterative process involving filter synthesis and yield estimation. Different design choices such as filter order, approximation, circuit topology, etc., affect the yield and also other parameters such as filter area, noise and dynamic range. The integrated environment offers effective mechanisms for exploring the design decision space to achieve the optimum in terms of yield and other design considerations. The paper describes the filter synthesis, yield estimation and optimization aspects of the system. The capabilities offered in the areas of data and flow management are also discussed. The results for a low pass filter design are presented.<>
一种内置可制造性设计的开关电容滤波综合系统
本文提出了一种以良率估计和优化为主要组成部分的开关电容滤波综合系统。设计过程是一个涉及滤波器合成和良率估计的迭代过程。不同的设计选择,如滤波器阶数、近似、电路拓扑等,会影响良率以及其他参数,如滤波面积、噪声和动态范围。集成环境为探索设计决策空间提供了有效的机制,从而在良率和其他设计考虑方面实现最佳。本文介绍了该系统的滤波器合成、良率估计和优化等方面。还讨论了数据和流管理领域提供的功能。最后给出了一个低通滤波器的设计结果。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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