ATPG with efficient testability measures and partial fault simulation

Abstract

Proposes an improved version of the test generation algorithm PODEM path oriented decision-making incorporating a different technique for backtracing and forward implication. The authors also propose a partial fault simulator which is integrated into the improved PODEM algorithm. The performance of this test generation package (when partial fault simulator is employed) is compared to that of a concurrent fault simulator using deterministically generated test patterns. It is shown that the runtime performance of the algorithm compares favourably with that of the concurrent fault simulator and is less memory intensive. The authors also present effective heuristics to determine some of the redundant faults and to drive the test vectors for some PI faults, by the use of implication relations. Experimental results on all the 10 ISCAS benchmark circuits demonstrate that the algorithm is faster and more efficient than the PODEM algorithm for these circuits.<>