Method for testable design and for built-in test

[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design Pub Date : 1991-01-04 DOI:10.1109/ISVD.1991.185136

P. Petrov

引用次数: 0

Abstract

The author proposes a method for testable design and for built-in test based on introduction of a new logical value in logic circuits. It is proved that only one (i) test is needed for detecting all constant multiple s-a-0/1 faults in any combinational (synchronous sequential) circuit where i is maximum sequential depth (MSD) of that circuit.<>

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可测试设计和内置测试方法

通过在逻辑电路中引入一种新的逻辑值，提出了一种测试设计和内置测试的方法。证明了在任意组合(同步顺序)电路中，当i为该电路的最大顺序深度(MSD)时，检测所有恒定多个s-a / 0/1故障只需要一个(i)测试

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design

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