{"title":"PLATEST: PLA测试发生器","authors":"T. Raghuram, M. Hasan","doi":"10.1109/ISVD.1991.185137","DOIUrl":null,"url":null,"abstract":"The growing use of PLAs in VLSI chips makes it imperative to have detailed study of the physical failures and the test generation. In this paper, physical failure analysis is carried out for NMOS PLA using SPICE simulation and the effects on the output of the PLA are studied. This study would be helpful in fault diagnosis and in improved design of the PLA. Based on these results the fault models are analysed and a novel test pattern generator, PLATEST, has been developed to generate minimal test set. PLATEST generates tests for all detectable cross-point faults and bridging faults. PLATEST has been implemented on a PC-AT in C(DOS).<<ETX>>","PeriodicalId":183602,"journal":{"name":"[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design","volume":"32 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"PLATEST: A PLA test generator\",\"authors\":\"T. Raghuram, M. Hasan\",\"doi\":\"10.1109/ISVD.1991.185137\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The growing use of PLAs in VLSI chips makes it imperative to have detailed study of the physical failures and the test generation. In this paper, physical failure analysis is carried out for NMOS PLA using SPICE simulation and the effects on the output of the PLA are studied. This study would be helpful in fault diagnosis and in improved design of the PLA. Based on these results the fault models are analysed and a novel test pattern generator, PLATEST, has been developed to generate minimal test set. PLATEST generates tests for all detectable cross-point faults and bridging faults. PLATEST has been implemented on a PC-AT in C(DOS).<<ETX>>\",\"PeriodicalId\":183602,\"journal\":{\"name\":\"[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design\",\"volume\":\"32 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1991-01-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISVD.1991.185137\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISVD.1991.185137","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The growing use of PLAs in VLSI chips makes it imperative to have detailed study of the physical failures and the test generation. In this paper, physical failure analysis is carried out for NMOS PLA using SPICE simulation and the effects on the output of the PLA are studied. This study would be helpful in fault diagnosis and in improved design of the PLA. Based on these results the fault models are analysed and a novel test pattern generator, PLATEST, has been developed to generate minimal test set. PLATEST generates tests for all detectable cross-point faults and bridging faults. PLATEST has been implemented on a PC-AT in C(DOS).<>
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