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Development of high-side capable thyristors in thin SOI technology 薄SOI技术中高侧能晶闸管的研制
2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD) Pub Date : 2013-05-26 DOI: 10.1109/ISPSD.2013.6694420
I. Emmerik-Weijland, R. van Dalen, A. B. van der Wal, M. Swanenberg
{"title":"Development of high-side capable thyristors in thin SOI technology","authors":"I. Emmerik-Weijland, R. van Dalen, A. B. van der Wal, M. Swanenberg","doi":"10.1109/ISPSD.2013.6694420","DOIUrl":"https://doi.org/10.1109/ISPSD.2013.6694420","url":null,"abstract":"In this paper we describe the development of integrated lateral thyristors in NXP's proprietary HV-SOI technology [1]. Thyristors are typically used for their extreme high-current capability or their zero-crossing switch-off, that allow easy implementation of phase-controlled power conversion. In this work, the main motivation to select thyristors is their ability to operate as an efficient switch under high-side (HS) conditions. The latter differs considerably from conventional thyristor operation, resulting in dedicated device optimisation. Also, the breakdown voltages (>650V) far exceed any previous work on thin SOI [2]. We present a detailed analysis of the thyristor operation and highlight the typical problems associated with the implementation on SOI.","PeriodicalId":175520,"journal":{"name":"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121099582","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
HCI-induced off-state I-V curve shifting and subsequent destruction in an STI-based LD-PMOS transistor 基于sti的LD-PMOS晶体管中hci诱导的非状态I-V曲线移位和随后的破坏
2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD) Pub Date : 2013-05-26 DOI: 10.1109/ISPSD.2013.6694425
H. Fujii, M. Ushiroda, K. Furuya, K. Onishi, Y. Yoshihisa, T. Ichikawa
{"title":"HCI-induced off-state I-V curve shifting and subsequent destruction in an STI-based LD-PMOS transistor","authors":"H. Fujii, M. Ushiroda, K. Furuya, K. Onishi, Y. Yoshihisa, T. Ichikawa","doi":"10.1109/ISPSD.2013.6694425","DOIUrl":"https://doi.org/10.1109/ISPSD.2013.6694425","url":null,"abstract":"This paper describes anomalous shifts of an off-state I-V curve that are found in an STI-based LD-PMOS, which includes degradation and recovery of breakdown voltage, increase in leakage current, and subsequent destruction under HCI stressing. Our experimental results suggest that the degradation and the recovery are caused by hot electrons injected into the STI around the bottom corner and the top corner, respectively, and all these hot electrons are responsible for the increase in leakage. The recovery is not desirable because the electrons injected into gate oxide near the STI top corner potentially cause destruction by a substrate hot electron (SHE) effect. We demonstrate that these shifts are controllable, and competitive performance of Rsp-BVoff trade-off has been achieved without them.","PeriodicalId":175520,"journal":{"name":"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116300718","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
700V thin SOI-LIGBT with high current capability 700V薄soi - light，具有大电流能力
2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD) Pub Date : 2013-05-26 DOI: 10.1109/ISPSD.2013.6694443
Jing Zhu, Weifeng Sun, Qinsong Qian, L. Cao, Nailong He, Sen Zhang
{"title":"700V thin SOI-LIGBT with high current capability","authors":"Jing Zhu, Weifeng Sun, Qinsong Qian, L. Cao, Nailong He, Sen Zhang","doi":"10.1109/ISPSD.2013.6694443","DOIUrl":"https://doi.org/10.1109/ISPSD.2013.6694443","url":null,"abstract":"The tridimensional channel SOI-LIGBT on 1.5μm thin SOI layer is developed in this paper. The key feature of the device is that there are numerous separated P-body cells located in the emitter region, which can increase the efficient channel width, enhance electron injection and attain a large current capability. The proposed SOI-LIGBT exhibits the current density of 150A/cm2, which has an improvement of 150% compared with the conventional structure. The SOI-LIGBT structure can be well applied in high voltage integrated circuit (HVIC).","PeriodicalId":175520,"journal":{"name":"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129849933","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
600V 1.3mμ·cm2 low-leakage low-current-collapse AlGaN/GaN HEMTs with AlN/SiNx passivation 600V 1.3 μ·cm2低漏低电流坍塌AlN/SiNx钝化AlGaN/GaN hemt
2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD) Pub Date : 2013-05-26 DOI: 10.1109/ISPSD.2013.6694478
Zhikai Tang, Sen Huang, Q. Jiang, Sheng-gen Liu, Cheng Liu, K. J. Chen
{"title":"600V 1.3mμ·cm2 low-leakage low-current-collapse AlGaN/GaN HEMTs with AlN/SiNx passivation","authors":"Zhikai Tang, Sen Huang, Q. Jiang, Sheng-gen Liu, Cheng Liu, K. J. Chen","doi":"10.1109/ISPSD.2013.6694478","DOIUrl":"https://doi.org/10.1109/ISPSD.2013.6694478","url":null,"abstract":"We report a new passivation technique that yields low OFF-state leakage current and greatly suppressed current collapse simultaneously in 600-V AlGaN/GaN high-electron-mobility transistors (HEMTs). This passivation structure consisted of an AlN/SiNx stack with 4-nm epitaxial AlN deposited by plasma-enhanced atomic layer deposition (PEALD) and 50-nm SiN<sub>x</sub> deposited by plasma-enhanced chemical vapor deposition (PECVD). The HEMTs with a gate-drain distance of 15 μm deliver a high maximum drain current of 900 mA/mm, a low OFF-state leakage current of 0.7 μA/mm at a drain bias (V<sub>DS</sub>) of 600 V, and a steep subthreshold slope of 63 mV/dec. Compared to the dc specific static ON-resistance (Static_R <sub>O</sub>N) of 1.3 mΩ cm<sup>2</sup>, the specific dynamic ON-resistance (Dyamic_R <sub>O</sub>N) after high OFF-state V<sub>DS</sub> stress at 650 V only increased to 2.1 mΩ·cm<sup>2</sup>. At elevated temperatures, the increase in Dyamic_ R<sub>O</sub>N was observed to be further suppressed - a highly desirable feature for power electronics applications.","PeriodicalId":175520,"journal":{"name":"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129686926","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Energy and current crowding limits in avalanche operation of IGBTs 雪崩运行中igbt的能量和电流拥挤限制
2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD) Pub Date : 2013-05-26 DOI: 10.1109/ISPSD.2013.6694439
M. Riccio, E. Napoli, A. Irace, G. Breglio, P. Spirito
{"title":"Energy and current crowding limits in avalanche operation of IGBTs","authors":"M. Riccio, E. Napoli, A. Irace, G. Breglio, P. Spirito","doi":"10.1109/ISPSD.2013.6694439","DOIUrl":"https://doi.org/10.1109/ISPSD.2013.6694439","url":null,"abstract":"The possible different failure modes that limit the maximum avalanche capability during unclamped inductive switching (UIS) in IGBTs is analyzed in this paper. Experimental measurements conducted on different commercial devices show that, at high peak current, the UIS limit moves from energy limitation to current limitation. This current driven failure mode is not well assessed in literature. In this contribution experimental results are provided and discussed with the target of determining experimental fingerprints that highlight different failure modes that affect IGBTs in avalanche operation. Moreover, the electrical waveforms of the UIS experiments are also exploited to provide clear indications on device operation mode.","PeriodicalId":175520,"journal":{"name":"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125436414","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A new type of SiC-VJFET with extreme low feedback capacitance 一种极低反馈电容的新型SiC-VJFET
2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD) Pub Date : 2013-05-26 DOI: 10.1109/ISPSD.2013.6694476
T. Ishikawa, Katsuya Nomura, T. Sugiyama, T. Uesugi, Koichi Nishikawa
{"title":"A new type of SiC-VJFET with extreme low feedback capacitance","authors":"T. Ishikawa, Katsuya Nomura, T. Sugiyama, T. Uesugi, Koichi Nishikawa","doi":"10.1109/ISPSD.2013.6694476","DOIUrl":"https://doi.org/10.1109/ISPSD.2013.6694476","url":null,"abstract":"In this paper, we propose a novel SiC vertical JFET (VJFET) with low feedback capacitance Crss by using a device simulator. A key feature of the proposed VJFET is the p+ screen grid inserted between gate and drain electrode. The screen grid is effective to reduce the Crss by 80% compared to conventional VJFETs. Due to the low Crss, total power loss of the proposed VJFET is the lowest among existing SiC power devices. This new VJFET can be a promising candidate for a high-speed and low-loss SiC power device.","PeriodicalId":175520,"journal":{"name":"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123012253","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
True 3D packaging solution for stacked vertical power devices 真正的3D封装解决方案，堆叠垂直电源器件
2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD) Pub Date : 2013-05-26 DOI: 10.1109/ISPSD.2013.6694405
N. Rouger, L. Benaissa, J. Widiez, B. Imbert, V. Gaude, S. Verrun, J. Crebier
{"title":"True 3D packaging solution for stacked vertical power devices","authors":"N. Rouger, L. Benaissa, J. Widiez, B. Imbert, V. Gaude, S. Verrun, J. Crebier","doi":"10.1109/ISPSD.2013.6694405","DOIUrl":"https://doi.org/10.1109/ISPSD.2013.6694405","url":null,"abstract":"This paper presents recent advances and breakthroughs of an alternative 3D packaging solution for vertical power devices. Direct bonding technology and trench isolation used for power device islanding are the cornerstone of this scheme of integration. Involving direct copper bonding layers, the technology is used during the mid-process to enable the wafer level bonding of vertical power devices to a joint metallic substrate while optimizing the devices intrinsic performances. Wafer level islanding and interconnect is used to simplify and guarantee the true 3D assembly at module level. This 3D assembly is based on the interconnect of matrices of low side and high side vertical power devices on top of each other. Our technology optimizes component surface height as well as alignments constraints. As a result, the true 3D integration of the active parts for power converters is optimized to the highest possible level, leading to strongly reduced EMI levels and increased switching speed capabilities. Key challenges, both on design, fabrication and implementation are presented, and the first prototypes based on four switching cells of vertical 500V power diodes and MOSFETs are introduced.","PeriodicalId":175520,"journal":{"name":"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122519679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Experimental investigation of transient electrical, thermal and mechanical behavior of IGBT inverter modules during operation IGBT逆变器模块运行过程中瞬态电、热、力学行为的实验研究
2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD) Pub Date : 2013-05-26 DOI: 10.1109/ISPSD.2013.6694467
B. Nagl, B. Czerny, M. Lederer, G. Khatibi, M. Thoben, J. Nicolics
{"title":"Experimental investigation of transient electrical, thermal and mechanical behavior of IGBT inverter modules during operation","authors":"B. Nagl, B. Czerny, M. Lederer, G. Khatibi, M. Thoben, J. Nicolics","doi":"10.1109/ISPSD.2013.6694467","DOIUrl":"https://doi.org/10.1109/ISPSD.2013.6694467","url":null,"abstract":"This study comprises the electrical analysis of an experimental investigation on thermo-mechanical vibration measurements on an IGBT inverter structure under operating conditions and shows a new way how to experience reliability relevant phenomena. In order to perform transient temperature measurements with IR thermography and optical vibration measurements one sub-system of the inverter module was extracted and operated at equivalent conditions. Necessary circuit modifications including parasitic impedances and their most important influences are discussed. The investigation revealed a strong dependence of the thermo-mechanical bonding wire vibrations on the inverter output frequency. At 1 Hz an amplitude of more than 4 μm was measured at the loop peak of a short bonding wire.","PeriodicalId":175520,"journal":{"name":"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125465100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Validated electro-thermal simulations of two different power MOSFET technologies and implications on their robustness 验证了两种不同功率MOSFET技术的电热仿真及其鲁棒性的影响
2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD) Pub Date : 2013-05-26 DOI: 10.1109/ISPSD.2013.6694414
S. de Filippis, R. Illing, M. Nelhiebel, S. Decker, H. Kock, A. Irace
{"title":"Validated electro-thermal simulations of two different power MOSFET technologies and implications on their robustness","authors":"S. de Filippis, R. Illing, M. Nelhiebel, S. Decker, H. Kock, A. Irace","doi":"10.1109/ISPSD.2013.6694414","DOIUrl":"https://doi.org/10.1109/ISPSD.2013.6694414","url":null,"abstract":"Power MOSFETs integrated in modern Smart Power switches feature a substantial high current capability due to the very low value of their transconductance coefficient K. In this paper we demonstrate that the trend related to the increasing current capability implies a reduced thermal stability range which may lead to less robust devices. Electro-thermal simulations of two test chips featuring two different technologies show that the higher the value of K, the less stable the device thermal behavior. Simulation results have been validated by means of temperature measurements performed using an integrated temperature sensor.","PeriodicalId":175520,"journal":{"name":"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"33 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120872762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
High temperature operation of diamond power SBD 金刚石动力SBD的高温操作
2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD) Pub Date : 2013-05-26 DOI: 10.1109/ISPSD.2013.6694477
H. Umezawa, Y. Kato, S. Shikata
{"title":"High temperature operation of diamond power SBD","authors":"H. Umezawa, Y. Kato, S. Shikata","doi":"10.1109/ISPSD.2013.6694477","DOIUrl":"https://doi.org/10.1109/ISPSD.2013.6694477","url":null,"abstract":"Vertical structured diamond Schottky barrier diodes with thick field plate have been developed. The diamond VSBD with 30μm Schottky electrode realizes low specific on-resistance and reverse voltage such as 9.4mOhm-cm<sup>2</sup> and 840V, respectively, even at 250°C. The Baliga's figure of limit (BV<sub>BD</sub><sup>2</sup>/R<sub>on</sub>S) is 75.1 MW/cm<sup>2</sup>, which is the best value in diamond diode at present. The diamond VSBD with 1,000μm Schottky electrode shows high forward current and low resistance such as more than 5 ampere and 0.6 Ohm, respectively, at 250°C. The estimated parasitic resistance of the SBD is less than 0.04 Ohm.","PeriodicalId":175520,"journal":{"name":"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115132742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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