发布求助
文献互助 智能选刊 最新文献

2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)最新文献

筛选
英文 中文
High performance, large-area, 1600 V / 150 A, 4H-SiC DMOSFET for robust high-power and high-temperature applications 高性能，大面积，1600 V / 150 A, 4H-SiC DMOSFET，适用于高功率和高温应用
2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD) Pub Date : 2013-05-26 DOI: 10.1109/ISPSD.2013.6694395
Lin Cheng, A. Agarwal, M. Schupbach, D. Gajewski, D. Lichtenwalner, V. Pala, S. Ryu, J. Richmond, J. Palmour, W. Ray, J. Schrock, A. Bilbao, S. Bayne, A. Lelis, C. Scozzie
{"title":"High performance, large-area, 1600 V / 150 A, 4H-SiC DMOSFET for robust high-power and high-temperature applications","authors":"Lin Cheng, A. Agarwal, M. Schupbach, D. Gajewski, D. Lichtenwalner, V. Pala, S. Ryu, J. Richmond, J. Palmour, W. Ray, J. Schrock, A. Bilbao, S. Bayne, A. Lelis, C. Scozzie","doi":"10.1109/ISPSD.2013.6694395","DOIUrl":"https://doi.org/10.1109/ISPSD.2013.6694395","url":null,"abstract":"In this paper, we report our recently developed 2<sup>nd</sup> Generation, large-area (56 mm<sup>2</sup> with an active conducting area of 40 mm<sup>2</sup>) 4H-SiC DMOSFET, which can reliably block 1600 V with very low leakage current under a gate-bias (V<sub>G</sub>) of 0 V at temperatures up to 200°C. The device also exhibits a low on-resistance (R<sub>ON</sub>) of 12.4 mΩ at 150 A and V<sub>G</sub> of 20 V. DC and dynamic switching characteristics of the SiC DMOSFET have also been compared with a commercially available 1200 V/ 200 A rated Si trench gate IGBT. The switching energy of the SiC DMOSFET at 600 V input voltage bus is > 4X lower than that of the Si IGBT at room-temperature and > 7X lower at 150°C. A comprehensive study on intrinsic reliability of this 2<sup>nd</sup> generation SiC MOSFET has been performed to build consumer confidence and to achieve broad market adoption of this disruptive power switch technology.","PeriodicalId":175520,"journal":{"name":"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"154 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122778262","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Increase of the Robustness of the junction terminations of power devices by a lateral variation of the Emitter Efficiency 通过发射极效率的横向变化增加功率器件结端的鲁棒性
2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD) Pub Date : 2013-05-26 DOI: 10.1109/ISPSD.2013.6694435
H. Schulze, J. Bauer, E. Falck, F. Niedernostheide, J. Biermann, T. Dutemeyer, O. Humbel, A. Schieber
{"title":"Increase of the Robustness of the junction terminations of power devices by a lateral variation of the Emitter Efficiency","authors":"H. Schulze, J. Bauer, E. Falck, F. Niedernostheide, J. Biermann, T. Dutemeyer, O. Humbel, A. Schieber","doi":"10.1109/ISPSD.2013.6694435","DOIUrl":"https://doi.org/10.1109/ISPSD.2013.6694435","url":null,"abstract":"A new diode technology called Emitter Controlled (EC)-HDR (High Dynamic Robustness) that allows a pronounced enhancement in switching safe-operating area has been developed. For the first time, the concept used for this drastic improvement is presented. The same principle has been applied to the Insulated Gate Bipolar Transistor (IGBT).","PeriodicalId":175520,"journal":{"name":"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117206046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
In depth thermal analysis of packaged GaN on Si power devices 对封装GaN基硅功率器件进行了深入的热分析
2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD) Pub Date : 2013-05-26 DOI: 10.1109/ISPSD.2013.6694406
Chieh-An Wang, Hsin-Ping Chou, Stone Cheng, Po-Chien Chou
{"title":"In depth thermal analysis of packaged GaN on Si power devices","authors":"Chieh-An Wang, Hsin-Ping Chou, Stone Cheng, Po-Chien Chou","doi":"10.1109/ISPSD.2013.6694406","DOIUrl":"https://doi.org/10.1109/ISPSD.2013.6694406","url":null,"abstract":"AlGaN/GaN high electron mobility transistors (HEMTs) are one of the prospective candidates for high switching frequency power electronics applications thanks to its wide band gap (3.4eV), high breakdown voltage, large critical electric field, high carrier mobility, and the inherent high speed characteristics. With the high power densities that AlGaN/GaN HEMTs are capable of reaching, heat dissipation is a crucial issue. This paper presents the thermal analysis of packaging development, the device is attached on a V-groove copper base, and mounted on TO-3P leadframe to enhance Si substrate thermal dissipation. The effects of structure design and fabrication processes on the device performance as well as thermal resistance were studied. In addition, micro-Raman/Infrared (IR) thermography was used to investigate temperature profiles and hot spot of the devices. Simulations provide key insights into device operation and the thermal mechanisms that affect reliability. After incorporating self-heating effect in calculations of current-voltage characteristics, our results agreed well with experimental data.","PeriodicalId":175520,"journal":{"name":"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"152 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116068140","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
800V lateral IGBT in bulk Si for low power compact SMPS applications 800V横向IGBT体硅，适用于低功耗紧凑SMPS应用
2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD) Pub Date : 2013-05-26 DOI: 10.1109/ISPSD.2013.6694430
T. Trajkovic, N. Udugampola, V. Pathirana, G. Camuso, F. Udrea, G. Amaratunga
{"title":"800V lateral IGBT in bulk Si for low power compact SMPS applications","authors":"T. Trajkovic, N. Udugampola, V. Pathirana, G. Camuso, F. Udrea, G. Amaratunga","doi":"10.1109/ISPSD.2013.6694430","DOIUrl":"https://doi.org/10.1109/ISPSD.2013.6694430","url":null,"abstract":"An 800V rated lateral IGBT for high frequency, low-cost off-line applications has been developed. The LIGBT features a new method of adjusting the bipolar gain, based on a floating N+ stripe in front of the P+ anode/drain region. The floating N+ layer enhances the carrier recombination at the anode/drain side of the drift region resulting in a very significant decrease in the turn-off speed and substantially lower overall losses. Switching speeds as low as 140ns at 25oC and 300ns at 125oC have been achieved with corresponding equivalent Rdson at 125oC below 90mΩ.cm2. A fully operational AC-DC converter using a controller with an integrated LIGBT+depletion mode MOSFET chip has been designed and qualified in plastic SOP8 packages and used in 5W, 65kHz SMPS applications. The device is fabricated in 0.6μm bulk silicon CMOS technology without any additional masking steps.","PeriodicalId":175520,"journal":{"name":"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127635082","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
High-voltage enhancement/Depletion-mode AlGaN/GaN HEMTs on modified SOI substrates 改性SOI衬底上的高压增强/耗尽模式AlGaN/GaN hemt
2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD) Pub Date : 2013-05-26 DOI: 10.1109/ISPSD.2013.6694431
Q. Jiang, Cheng Liu, Yunyou Lu, K. J. Chen
{"title":"High-voltage enhancement/Depletion-mode AlGaN/GaN HEMTs on modified SOI substrates","authors":"Q. Jiang, Cheng Liu, Yunyou Lu, K. J. Chen","doi":"10.1109/ISPSD.2013.6694431","DOIUrl":"https://doi.org/10.1109/ISPSD.2013.6694431","url":null,"abstract":"High-voltage AlGaN/GaN HEMTs fabricated on a GaN-on-SOI platform were demonstrated. The GaN-on-SOI wafer features III-nitride epi-layers grown by MOCVD on a modified SOI wafer consisting of a p-type (111) Si device layer, a SiO2 buried oxide and a p-type (100) Si handle substrate. Depletion- and enhancementmode HEMTs are monolithically integrated. The Enhancement-mode HEMTs obtained by fluorine plasma implantation technique deliver large ON/OFF current ratio (107), large breakdown voltage (1354 V with floating substrate) and low ON-resistance (3.9 mΩ·cm2). In addition, the impact of the buried oxide on thermal dissipation is estimated by a simple thermal resistance model.","PeriodicalId":175520,"journal":{"name":"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132181131","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
600 V-class trench-filling super junction power MOSFETs for low loss and low leakage current 600 v级沟槽填充超级结功率mosfet，具有低损耗和低漏电流
2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD) Pub Date : 2013-05-26 DOI: 10.1109/ISPSD.2013.6694457
Yuma Kagata, Y. Oda, K. Hayashi, N. Akagi, T. Shibata, K. Eguchi, Tsuyoshi Yamamoto, H. Yamaguchi
{"title":"600 V-class trench-filling super junction power MOSFETs for low loss and low leakage current","authors":"Yuma Kagata, Y. Oda, K. Hayashi, N. Akagi, T. Shibata, K. Eguchi, Tsuyoshi Yamamoto, H. Yamaguchi","doi":"10.1109/ISPSD.2013.6694457","DOIUrl":"https://doi.org/10.1109/ISPSD.2013.6694457","url":null,"abstract":"Trench-filling technology realizes an outstanding productivity for fabricating the Super Junction (SJ) structure of SJ-MOSFETs. However, crystal defects that occur during epitaxial growth are causing poor electrical characteristics. Our optimized process reduced the number of crystal defects from over 2000/mm2 to under 10/mm2. As a result, we have achieved both low loss and low leakage current and high ruggedness for the first time with the SJ-MOSFET fabricated by the trench filling epitaxial growth technique. The drain leakage current decreased from tens of micro amperes to tens of nano amperes. The improved SJ-MOSFET has achieved an avalanche current of 35 A, a specific on-resistance (RonA) of 13.5 mΩcm2, an output capacitance stored energy (Eoss) of 10.3 μJ, and a diode commutation speed (di/dt) of over 2000 A/μs, respectively.","PeriodicalId":175520,"journal":{"name":"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132372018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A 4H-SiC trench MOSFET with thick bottom oxide for improving characteristics 一种采用厚底氧化物的4H-SiC沟槽MOSFET
2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD) Pub Date : 2013-05-26 DOI: 10.1109/ISPSD.2013.6694394
H. Takaya, J. Morimoto, K. Hamada, T. Yamamoto, J. Sakakibara, Y. Watanabe, N. Soejima
{"title":"A 4H-SiC trench MOSFET with thick bottom oxide for improving characteristics","authors":"H. Takaya, J. Morimoto, K. Hamada, T. Yamamoto, J. Sakakibara, Y. Watanabe, N. Soejima","doi":"10.1109/ISPSD.2013.6694394","DOIUrl":"https://doi.org/10.1109/ISPSD.2013.6694394","url":null,"abstract":"A 4H-SiC trench MOSFET has been developed that features the use of trench gates with a thick oxide layer on the bottoms of the trenches for relieving the electric field strength of the gate oxide layer. The maximum electric field strength and gate-drain charge (Qgd) of this device is 46% and 38% lower than that of a conventional MOSFET, respectively. A □5mm chip was fabricated with a thick oxide layer under the trench. The drain-source breakdown voltage (BVdss) of this chip is 1400V and the specific on-resistance (Ron.sp) is 4.4mΩcm2 (Vg=20V, Vd=2V). A high breakdown voltage is obtained by a wide trench terminal structure and trench separation.","PeriodicalId":175520,"journal":{"name":"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128672509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
Lateral tapered active field-plate LDMOS device for 20V application in thin-film SOI 用于20V薄膜SOI的横向锥形有源场极板LDMOS器件
2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD) Pub Date : 2013-05-26 DOI: 10.1109/ISPSD.2013.6694464
M. Abou-Khalil, T. Letavic, J. Slinkman, A. Joseph, A. Botula, M. Jaffe
{"title":"Lateral tapered active field-plate LDMOS device for 20V application in thin-film SOI","authors":"M. Abou-Khalil, T. Letavic, J. Slinkman, A. Joseph, A. Botula, M. Jaffe","doi":"10.1109/ISPSD.2013.6694464","DOIUrl":"https://doi.org/10.1109/ISPSD.2013.6694464","url":null,"abstract":"We present a new device design for 20V application in thin body SOI technology. High breakdown voltage is achieved by forming RX-bound field plates which deplete the drift region of an LDMOS structure using only lateral electric field coupling. A baseline 180nm CMOS SOI process is utilized and RX field plate shapes are designed to result in an essentially uniform longitudinal drift region electric field satisfying the RESURF principal. We studied device scaling and the effect of varying the width and length of the angular RX field plates and their relation to impact ionization rate in both floating body and body-contacted n-channel LDMOS deices. 3D TCAD simulations were used to investigate the effect design parameters on electric field and impact ionization. Unitary 20V rated-LDMOS devices are experimentally demonstrated, verifying a LDMOS option to stacked CMOS for high voltage applications in SOI technology.","PeriodicalId":175520,"journal":{"name":"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130756706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Physics-based analytical model for high-voltage bidirectional GaN transistors using lateral GaN power HEMT 基于物理的横向GaN功率HEMT高压双向GaN晶体管分析模型
2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD) Pub Date : 2013-05-26 DOI: 10.1109/ISPSD.2013.6694483
J. Waldron, T. Chow
{"title":"Physics-based analytical model for high-voltage bidirectional GaN transistors using lateral GaN power HEMT","authors":"J. Waldron, T. Chow","doi":"10.1109/ISPSD.2013.6694483","DOIUrl":"https://doi.org/10.1109/ISPSD.2013.6694483","url":null,"abstract":"A bidirectional switching GaN transistor, PCB-packaged using commercially available high voltage power GaN HEMTs (200V, 3A) from EPC, has been modeled and characterized. A physics-based FET model, originally developed by Statz for short-channel GaAs MESFET, has been adapted to model both static and switching characteristics of both the constituent HEMT and the bidirectional switch up to 125°C. We have found that the Statz model is superior to conventional short-channel MOSFET models due to the mixed pentode-triode on-state I-V characteristics of the EPC GaN HEMT. The bidirectional GaN transistor exhibits linear operation as well as bidirectional current saturation, offering low on-state resistance along with current limiting capabilities.","PeriodicalId":175520,"journal":{"name":"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121351508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 30
Dynamic self-clamping at short-circuit turn-off of high-voltage IGBTs 高压igbt短路关断时的动态自箝位
2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD) Pub Date : 2013-05-26 DOI: 10.1109/ISPSD.2013.6694440
T. Basler, Riteshkumar Bhojani, J. Lutz, R. Jakob
{"title":"Dynamic self-clamping at short-circuit turn-off of high-voltage IGBTs","authors":"T. Basler, Riteshkumar Bhojani, J. Lutz, R. Jakob","doi":"10.1109/ISPSD.2013.6694440","DOIUrl":"https://doi.org/10.1109/ISPSD.2013.6694440","url":null,"abstract":"Measurements show that the IGBT is able to clamp the collector-emitter voltage to a certain value at short-circuit turn-off despite a very low gate turn-off resistor in combination with a high parasitic inductance is applied. The IGBT itself reduces the turn-off diC/dt by avalanche injection. However, device destructions during fast turn-off were observed which cannot be linked with an overvoltage failure mode. Measurements and semiconductor simulations of high-voltage IGBTs explain the self-clamping mechanism in detail. Possible failures which can be connected with filamentation processes are described. Options for improving the IGBT robustness during short-circuit turn-off are discussed.","PeriodicalId":175520,"journal":{"name":"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124420245","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：481959085
Book学术官方微信