一种极低反馈电容的新型SiC-VJFET

2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD) Pub Date : 2013-05-26 DOI:10.1109/ISPSD.2013.6694476

T. Ishikawa, Katsuya Nomura, T. Sugiyama, T. Uesugi, Koichi Nishikawa

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引用次数: 2

摘要

本文利用器件模拟器设计了一种低反馈电容交叉的新型SiC垂直JFET (VJFET)。所提出的VJFET的一个关键特征是在栅极和漏极之间插入p+屏栅。与传统的vjfet相比，屏幕网格有效地减少了80%的交叉。由于低交叉，所提出的VJFET的总功率损耗是现有SiC功率器件中最低的。这种新的VJFET可以成为高速低损耗SiC功率器件的有希望的候选者。

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A new type of SiC-VJFET with extreme low feedback capacitance

In this paper, we propose a novel SiC vertical JFET (VJFET) with low feedback capacitance Crss by using a device simulator. A key feature of the proposed VJFET is the p+ screen grid inserted between gate and drain electrode. The screen grid is effective to reduce the Crss by 80% compared to conventional VJFETs. Due to the low Crss, total power loss of the proposed VJFET is the lowest among existing SiC power devices. This new VJFET can be a promising candidate for a high-speed and low-loss SiC power device.

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来源期刊

2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)

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