1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325)最新文献

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Highly reliable MIM capacitor technology using low pressure CVD-WN cylinder storage-node for 0.12 /spl mu/m-scale embedded DRAM 采用低压CVD-WN圆柱存储节点的高可靠性MIM电容技术,用于0.12 /spl mu/m级嵌入式DRAM
S. Kamiyama, J. M. Drynan, Y. Takaishi, K. Koyama
{"title":"Highly reliable MIM capacitor technology using low pressure CVD-WN cylinder storage-node for 0.12 /spl mu/m-scale embedded DRAM","authors":"S. Kamiyama, J. M. Drynan, Y. Takaishi, K. Koyama","doi":"10.1109/VLSIT.1999.799329","DOIUrl":"https://doi.org/10.1109/VLSIT.1999.799329","url":null,"abstract":"A metal-insulator-metal (MIM) capacitor process technology has been developed using highly reliable ultra-thin Ta/sub 2/O/sub 5/ capacitors with low pressure CVD-WN cylinder storage-nodes for 0.12 /spl mu/m-scale embedded DRAMs. The CVD-WN films using WF/sub 6/ and NF/sub 3/ gases have excellent characteristics with respect to surface morphology and step coverage in comparison with CVD-W films. As a result, the cell capacitance with CVD-WN cylinder storage-nodes is increased to 1.5 times as large as that of CVD-W cylinder storage-nodes. The CVD-WN cylinder capacitors can realize a 30 fF/cell capacitance with 0.6 /spl mu/m-height storage-nodes in an area of 0.25/spl times/0.5 /spl mu/m/sup 2/.","PeriodicalId":171010,"journal":{"name":"1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129337349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Fully functional 0.5-/spl mu/m 64-kbit embedded SBT FeRAM using a new low temperature SBT deposition technique 全功能0.5-/spl mu/m 64 kbit嵌入式SBT FeRAM采用新的低温SBT沉积技术
T. Eshita, K. Nakamura, M. Mushiga, A. Itho, S. Miyagaki, H. Yamawaki, M. Aoki, S. Kishii, Y. Arimoto
{"title":"Fully functional 0.5-/spl mu/m 64-kbit embedded SBT FeRAM using a new low temperature SBT deposition technique","authors":"T. Eshita, K. Nakamura, M. Mushiga, A. Itho, S. Miyagaki, H. Yamawaki, M. Aoki, S. Kishii, Y. Arimoto","doi":"10.1109/VLSIT.1999.799382","DOIUrl":"https://doi.org/10.1109/VLSIT.1999.799382","url":null,"abstract":"0.5 /spl mu/m design rule embedded 64 kbit SBT (SrBi/sub 2/(Ta,Nb)/sub 2/O/sub 9/) FeRAMs (ferroelectric RAM) are fabricated using a new low temperature SBT deposition technique. The developed deposition technique has successfully lowered SBT crystallization temperature from 800/spl deg/C to 700/spl deg/C, resulting in co-fabrication of FeRAM and fine CMOS logic devices with W plugs. The fabricated devices are proven to be fully functional.","PeriodicalId":171010,"journal":{"name":"1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132940592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 0.15-/spl mu/m/73-GHz f/sub max/ RF BiCMOS technology using cobalt silicide ring extrinsic-base structure 采用硅化钴环外基结构的0.15-/spl mu/m/73-GHz f/sub max/ RF BiCMOS技术
H. Suzuki, H. Yoshida, Y. Kinoshita, H. Fujii, T. Yamazaki
{"title":"A 0.15-/spl mu/m/73-GHz f/sub max/ RF BiCMOS technology using cobalt silicide ring extrinsic-base structure","authors":"H. Suzuki, H. Yoshida, Y. Kinoshita, H. Fujii, T. Yamazaki","doi":"10.1109/VLSIT.1999.799387","DOIUrl":"https://doi.org/10.1109/VLSIT.1999.799387","url":null,"abstract":"This paper presents an advanced RF mixed-signal BiCMOS technology. A single-polysilicon bipolar transistor with a high maximum frequency of oscillation (f/sub max/) is successfully implemented into a 0.15 /spl mu/m dual gate CMOS process. To achieve such a bipolar transistor, a cobalt silicide (CoSi/sub 2/) ring-shaped extrinsic-base structure is newly developed. This bipolar transistor demonstrates 73 GHz f/sub max/, minimum noise figure (NF/sub min/) of 1.1 dB and a cut-off frequency emitter-to-collector breakdown voltage (f/sub T//spl middot/BV/sub CEO/) product of 160 GHz/spl middot/V, which is competitive with previously reported SiGe-based technology.","PeriodicalId":171010,"journal":{"name":"1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325)","volume":"123 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134646014","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A novel simple shallow trench isolation (SSTI) technology using high selective CeO/sub 2/ slurry and liner SiN as a CMP stopper 一种新型的简单浅沟隔离(SSTI)技术,使用高选择性的CeO/sub - 2/泥浆和尾管SiN作为CMP堵塞剂
T. Park, J.Y. Kim, K.W. Park, H. Lee, H. Shin, Y. Kim, M.H. Park, H. Kang, M.Y. Lee
{"title":"A novel simple shallow trench isolation (SSTI) technology using high selective CeO/sub 2/ slurry and liner SiN as a CMP stopper","authors":"T. Park, J.Y. Kim, K.W. Park, H. Lee, H. Shin, Y. Kim, M.H. Park, H. Kang, M.Y. Lee","doi":"10.1109/VLSIT.1999.799392","DOIUrl":"https://doi.org/10.1109/VLSIT.1999.799392","url":null,"abstract":"A novel simple shallow trench isolation technology, SSTI, has been developed. SSTI consists of direct trench etching masked only with the photoresist, trench oxidation, liner SiN deposition, CVD oxide trench fill, densification, and high selectivity CMP. CMP stops at the liner SiN with a residual SiN thickness range of less than 2 nm and without micro-scratching. High selectivity CMP eliminates the field recess variation which is one of the drawbacks of conventional STI. SSTI is a promising candidate for future isolation technology.","PeriodicalId":171010,"journal":{"name":"1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114495820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Submicron CMOS thermal noise modeling from an RF perspective 基于射频视角的亚微米CMOS热噪声建模
J.J. Ou, Xiaodong Jin, Chenming Hu, P. Gray
{"title":"Submicron CMOS thermal noise modeling from an RF perspective","authors":"J.J. Ou, Xiaodong Jin, Chenming Hu, P. Gray","doi":"10.1109/VLSIT.1999.799388","DOIUrl":"https://doi.org/10.1109/VLSIT.1999.799388","url":null,"abstract":"Continuous scaling of submicron CMOS technologies will soon make low cost, wireless system-on-a-chip communication products possible. The ultimate goal of these systems is to integrate the entire RF front-end with DSP together on a single chip. One key issue to the success of this CMOS RF system LSI chip implementation is how to accurately predict circuit performance using simulators such as SPICE. This will require accurate RF AC and noise models. The latter is essential for optimizing the noise performance which will in turn lead to a low power design. Recently, several CMOS RF models have been proposed for improvement on the accuracy of AC analysis at high frequencies (Ou et al, 1998). However, the accuracy of the existing noise models is not satisfactory for submicron CMOS. In this paper, a physics-based RF thermal noise model is proposed for submicron CMOS devices with a channel thermal noise model, resulting in a nearly bias-independent noise factor /spl gamma/. This model shows good agreement with measured RF noise data across a wide range of bias conditions.","PeriodicalId":171010,"journal":{"name":"1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116926631","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
High performance and highly reliable deep submicron CMOSFETs using nitrided-oxide 高性能和高可靠的深亚微米cmosfet使用氮化氧化物
K. Irino, Y. Tamura, T. Nakanishi, M. Shigeno, K. Hikazutani, M. Higashi, K. Takasaki
{"title":"High performance and highly reliable deep submicron CMOSFETs using nitrided-oxide","authors":"K. Irino, Y. Tamura, T. Nakanishi, M. Shigeno, K. Hikazutani, M. Higashi, K. Takasaki","doi":"10.1109/VLSIT.1999.799371","DOIUrl":"https://doi.org/10.1109/VLSIT.1999.799371","url":null,"abstract":"High performance and highly reliable CMOSFETs have been obtained using newly-developed nitrided-oxide processing, which features the localization of the nitrogen profile at the SiO/sub 2/-Si interface, and giving different nitrogen concentrations between the gate and LDD area. In p-MOSFETs, I/sub on/ can be increased by 12%, and I/sub off/ can be decreased by 50% compared with pure oxide. Also, in n-MOSFETs, hot carrier reliability significantly improves.","PeriodicalId":171010,"journal":{"name":"1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129436286","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Device and reliability of high-k Al/sub 2/O/sub 3/ gate dielectric with good mobility and low D/sub it/ 器件和可靠性高k Al/sub 2/O/sub 3/栅极电介质具有良好的迁移率和低D/sub it/
A. Chin, C. Liao, C.H. Lu, W. Chen, C. Tsai
{"title":"Device and reliability of high-k Al/sub 2/O/sub 3/ gate dielectric with good mobility and low D/sub it/","authors":"A. Chin, C. Liao, C.H. Lu, W. Chen, C. Tsai","doi":"10.1109/VLSIT.1999.799380","DOIUrl":"https://doi.org/10.1109/VLSIT.1999.799380","url":null,"abstract":"We report a very simple process to fabricate Al/sub 2/O/sub 3/ gate dielectric for CMOS technology with k (9.0 to 9.8) greater than Si/sub 3/N/sub 4/. Al/sub 2/O/sub 3/ is formed by direct oxidation from thermally evaporated Al. The 48 /spl Aring/ Al/sub 2/O/sub 3/ has /spl sim/7 orders lower leakage current than equivalent 21 /spl Aring/ SiO/sub 2/. A good Al/sub 2/O/sub 3/-Si interface was evidenced by the low interface density of 1/spl times/10/sup 11/ eVcm/sup -2/ and compatible electron mobility with thermal SiO/sub 2/. Good reliability is measured from the small stress induced leakage current (SILC) after 2.5 V stress for 10,000 s.","PeriodicalId":171010,"journal":{"name":"1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130148259","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
Node connection/quantum phase-shifting mask-path to below 0.3-/spl mu/m pitch, proximity effect free random interconnect and memory patterning 节点连接/量子相移掩膜路径低于0.3-/spl mu/m间距,邻近效应无随机互连和记忆模式
Hiroshi Fukuda
{"title":"Node connection/quantum phase-shifting mask-path to below 0.3-/spl mu/m pitch, proximity effect free random interconnect and memory patterning","authors":"Hiroshi Fukuda","doi":"10.1116/1.590997","DOIUrl":"https://doi.org/10.1116/1.590997","url":null,"abstract":"New design concepts for alternating phase-shifting masks are proposed which enable the alternating PSMs to be applied to random patterns with the least design restrictions and reduced proximity effects. Original design patterns are decomposed to several sub-patterns using geometrical operations, so that each sub-pattern can be achieved by the alternating type PSMs. The possibility of patterning sub-0.3 /spl mu/m pitch random interconnects with conventional DUV tools is shown.","PeriodicalId":171010,"journal":{"name":"1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127958234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Smart pockets-total suppression of roll-off and roll-up [MOSFET doping] 智能口袋-完全抑制滚出和卷起[MOSFET掺杂]
R. Gwoziecki, T. Skotnicki
{"title":"Smart pockets-total suppression of roll-off and roll-up [MOSFET doping]","authors":"R. Gwoziecki, T. Skotnicki","doi":"10.1109/VLSIT.1999.799355","DOIUrl":"https://doi.org/10.1109/VLSIT.1999.799355","url":null,"abstract":"We have demonstrated that with use of pocket implants, there exists an asymptotic threshold voltage-gate length (V/sub th/-L) curve which can only be shifted to shorter device lengths if a larger amount of roll-up and steeper roll-off are allowed. This inherent feature of conventional pockets narrows the technological window for sub-0.1 /spl mu/m MOSFETs. Therefore, we propose a new concept called \"smart pockets\", enabling total annihilation of roll-up and roll-off and thus offering a perfectly flat V/sub th/-L dependence down to the desired gate length.","PeriodicalId":171010,"journal":{"name":"1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130410130","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
A novel high performance and reliability p-type floating gate n-channel flash EEPROM 一种新型高性能、可靠性高的p型浮栅n通道闪存EEPROM
S.S. Chung, C. Yih, S. Liaw, Z. Ho, S.S. Wu, C. Lin, D. Kuo, M. Liang
{"title":"A novel high performance and reliability p-type floating gate n-channel flash EEPROM","authors":"S.S. Chung, C. Yih, S. Liaw, Z. Ho, S.S. Wu, C. Lin, D. Kuo, M. Liang","doi":"10.1109/VLSIT.1999.799319","DOIUrl":"https://doi.org/10.1109/VLSIT.1999.799319","url":null,"abstract":"In the design of either n-channel or p-channel flash memory, a conventional n-type poly-Si floating gate (Tam et al., 1988; Ohnakado et al., 1995; Hsu et al., 1992; Chung et al., 1997) is normally used. None has been reported using p-type as a floating gate in these cells. Recently, p-type polysilicon gate technology in a dual gate CMOS process with p/sup +/ polysilicon gate has matured (Kurio et al., 1993). On the other hand, multi-level memory cell technology for bit cost reduction has gained a lot of interest (Aritome et al., 1995; Kencke et al., 1996). One major requirement is that the threshold voltage distributions for various states must be separated to avoid read errors. However, widely spread distributions need higher programming voltages. In this paper, we propose for the first time use of p-type polysilicon as the floating gate in an n-channel flash memory in order to improve the cell performance and reliability. Results show that the flash cell with p-type floating gate has much better performance by comparison with conventional n-type floating-gate structures, such as faster programming/erase speed, larger operating window, better read-disturb and endurance characteristics. Successful application of this flash memory cell for multi-level operation is also demonstrated.","PeriodicalId":171010,"journal":{"name":"1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130494380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
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