1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325)最新文献

Future perspective and scaling down roadmap for RF CMOS RF CMOS的未来展望和缩小路线图

1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325) Pub Date : 1999-06-17 DOI: 10.1109/VLSIC.1999.797271

E. Morifuji, H. Momose, T. Ohguro, T. Yoshitomi, H. Kimijima, Fumiyoshi Matsuoka, M. Kinugawa, Y. Katsumata, Hiroshi Iwai

引用次数: 102

Monte Carlo modeling of threshold variation due to dopant fluctuations 由掺杂剂波动引起的阈值变化的蒙特卡罗模型

1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325) Pub Date : 1999-06-17 DOI: 10.1109/VLSIC.1999.797274

D. Frank, Y. Taur, M. Ieong, H.-S.P. Wong

引用次数: 91

Low-temperature metal/ON/HSG-cylinder capacitor process for high density embedded DRAMs 高密度嵌入式dram的低温金属/ON/ hsg圆柱体电容器工艺

1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325) Pub Date : 1999-06-14 DOI: 10.1109/VLSIT.1999.799391

I. Yamamoto, I. Honma, T. Yamamoto, K. Urabe, K. Inoue, Y. Takaishi, Y. Yamada, K. Tokunaga, R. Kubota, M. Hamada, Y. Kato

引用次数: 1

Re-distribution of Cu contamination in advanced high-speed CMOS and its influence on device characteristics 先进高速CMOS中Cu污染的再分布及其对器件特性的影响

1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325) Pub Date : 1999-06-14 DOI: 10.1109/VLSIT.1999.799377

K. Hozawa, T. Itoga, S. Isomae, M. Ohkura

{"title":"Re-distribution of Cu contamination in advanced high-speed CMOS and its influence on device characteristics","authors":"K. Hozawa, T. Itoga, S. Isomae, M. Ohkura","doi":"10.1109/VLSIT.1999.799377","DOIUrl":"https://doi.org/10.1109/VLSIT.1999.799377","url":null,"abstract":"Cu contamination will be a crucial concern in advanced high-speed CMOS fabrication using Cu wiring. We evaluated the Cu gettering efficiency of Si wafers quantitatively by counting the Cu atoms that diffused from the backside to the front side of wafers through direct observation using TXRF (total reflection X-ray fluorescence). From this evaluation, we estimated the Cu gettering efficiency of the boron-doped Si layer and the Cu contamination redistribution behavior within a CMOS device. We found that even when the Cu contamination exists only on the Si wafer backside, about half of the Cu atoms diffuse to and segregate at the front surface during annealing. They are also found to segregate in the high concentration (>10/sup 17//cm/sup 3/) boron-doped layers which are used as components of a CMOS structure, such as the p-type well and the source/drain. These segregated Cu atoms will drastically degrade the CMOS device characteristics. The obtained results indicate that Si wafers with high gettering ability and Cu contamination control are indispensable for highly reliable CMOS devices.","PeriodicalId":171010,"journal":{"name":"1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129948370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

A DRAM technology using MIM BST capacitor for 0.15 /spl mu/m DRAM generation and beyond 一种采用MIM BST电容的DRAM技术，可产生0.15 /spl mu/m以上的DRAM

1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325) Pub Date : 1999-06-14 DOI: 10.1109/VLSIT.1999.799326

K.N. Kim, D. Kwak, Y. Hwang, G. Jeong, T. Chung, B.J. Park, Y. Chun, J. Oh, C. Yoo, B. Joo

引用次数: 3

A source/drain formation technology utilizing sub-10 keV arsenic and assist-phosphorus implantation for 0.13 /spl mu/m MOSFET 利用低于10 keV的砷和辅助磷注入0.13 /spl mu/m MOSFET的源/漏形成技术

1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325) Pub Date : 1999-06-14 DOI: 10.1109/VLSIT.1999.799335

K. Imai, S. Shishiguchi, K. Yamaguchi, N. Kimizuka, H. Onishi, T. Horiuchi

引用次数: 4

Co salicide compatible 2-step activation annealing process for deca-nano scaled MOSFETs 十纳米尺度mosfet的二步活化退火工艺

1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325) Pub Date : 1999-06-14 DOI: 10.1109/VLSIT.1999.799334

K. Goto, Y. Sambonsugi, T. Sugii

引用次数: 6

A FRAM technology using 1T1C and triple metal layers for high performance and high density FRAMs 一种采用1T1C和三金属层的FRAM技术，用于高性能高密度FRAM

1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325) Pub Date : 1999-06-14 DOI: 10.1109/VLSIT.1999.799383

S.Y. Lee, D. Jung, Y.J. Song, B. Koo, S.O. Park, H. Cho, S.J. Oh, D. Hwang, S.I. Lee, J. Lee, Y.S. Park, I.S. Jung, Kinam Kim

{"title":"A FRAM technology using 1T1C and triple metal layers for high performance and high density FRAMs","authors":"S.Y. Lee, D. Jung, Y.J. Song, B. Koo, S.O. Park, H. Cho, S.J. Oh, D. Hwang, S.I. Lee, J. Lee, Y.S. Park, I.S. Jung, Kinam Kim","doi":"10.1109/VLSIT.1999.799383","DOIUrl":"https://doi.org/10.1109/VLSIT.1999.799383","url":null,"abstract":"Recently, ferroelectric random access memory has drawn a great deal of attention due to inherent properties such as nonvolatility, long retention time, high endurance, fast access time, small cell size compared to DRAM cell size in principle, and strong resistance to /spl alpha/-particle and cosmic ray irradiation. None of the available commercial memories meet all of the properties of the ferroelectric memory. Although ferroelectric memory has inherent good properties, full utilization of these properties has not yet been realized. Commercially available products are limited to low densities. The commercially available ferroelectric memory uses a 2T2C (two transistor-two capacitor) structure with single level metal instead of a 1T1C (one transistor-one capacitor) structure with multiple metal layers which is believed to be essential for mega-bit or giga-bit density memory. In this paper, an integration technology for high performance and high density FRAMs is developed using a 1T1C robust capacitor in a COB (capacitor over bit line) structure with triple metallization processes. The technology developed in this paper is evaluated with an experimental 4 Mb FRAM, which is the highest FRAM density developed to date.","PeriodicalId":171010,"journal":{"name":"1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115335668","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

Novel bi-directional tunneling NOR (BiNOR) type 3-D flash memory cell 新型双向隧道NOR (BiNOR)型三维快闪存储单元

1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325) Pub Date : 1999-06-14 DOI: 10.1109/VLSIT.1999.799352

E. Yang, Cheng-Jye Liu, Tien-Sheng Chao, Ming-Chi Liaw, C. Hsu

引用次数: 3

Temperature acceleration of oxide breakdown and its impact on ultra-thin gate oxide reliability 氧化物击穿温度加速及其对超薄栅极氧化物可靠性的影响

1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325) Pub Date : 1999-06-14 DOI: 10.1109/VLSIT.1999.799339

R. Degraeve, N. Pangon, B. Kaczer, T. Nigam, G. Groeseneken, A. Naem

引用次数: 61