A source/drain formation technology utilizing sub-10 keV arsenic and assist-phosphorus implantation for 0.13 /spl mu/m MOSFET

Abstract

We have developed a novel technology for formation of source/drain regions in 0.13 /spl mu/m MOSFETs. A combination of low-energy arsenic (8 keV) implantation and assist-phosphorous implantation suppresses transient enchanted diffusion (TED) of boron, and this improves I/sub on/-I/sub off/ characteristics as well as V/sub th/ roll-off. Assisted by low-dose phosphorous implantation, this technology can minimize both junction-leakage current and gate-poly depletion. An I/sub dsat/ of an nMOSFET of 750 /spl mu/A//spl mu/m (with t/sub ox//sup inv/ of 3.3 nm at 1.5 V) was obtained.