1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325)最新文献

筛选
英文 中文
A self-aligned split-gate flash EEPROM cell with 3-D pillar structure 一种具有三维柱状结构的自对准分栅闪存EEPROM单元
F. Hayashi, J. Plummer
{"title":"A self-aligned split-gate flash EEPROM cell with 3-D pillar structure","authors":"F. Hayashi, J. Plummer","doi":"10.1109/VLSIT.1999.799353","DOIUrl":"https://doi.org/10.1109/VLSIT.1999.799353","url":null,"abstract":"A novel 3D memory cell has been proposed for high density future generation flash EEPROMs. A self-aligned split-gate (SASG) structure, minimizing the split-gate length, has been implemented in a pillar-shape cell with high scalability over the tunnel oxide scaling limitation. This cell technology allows an ideal split-gate cell size of 6F/sup 2/. Good programming and erase characteristics have been obtained and over-erasing has been suppressed down to a 0.1 /spl mu/m split-gate length in experimental devices.","PeriodicalId":171010,"journal":{"name":"1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131603034","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Minimizing body instability in deep sub-micron SOI MOSFETs for sub-1 V RF applications 在亚1 V以下射频应用中,最大限度地减少深亚微米SOI mosfet的体稳定性
Y. Tseng, W.M. Huang, M. Mendicino, P. Welch, V. Ilderem, J. Woo
{"title":"Minimizing body instability in deep sub-micron SOI MOSFETs for sub-1 V RF applications","authors":"Y. Tseng, W.M. Huang, M. Mendicino, P. Welch, V. Ilderem, J. Woo","doi":"10.1109/VLSIT.1999.799323","DOIUrl":"https://doi.org/10.1109/VLSIT.1999.799323","url":null,"abstract":"We report an extensive study on the SOI body instability and the noise constraint dependence on device scaling for sub-1 V RF SOI CMOS applications. Also, the device parameters associated with these issues are addressed.","PeriodicalId":171010,"journal":{"name":"1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325)","volume":"220 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123094421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
High performance Cu interconnects with low-k BCB-polymers by plasma-enhanced monomer-vapor polymerization (PE-MVP) method 采用等离子体增强单体气相聚合(PE-MVP)方法实现低钾bcb聚合物与高性能Cu互连
J. Kawahara, A. Nakano, S. Saito, K. Kinoshita, T. Onodera, Y. Hayashi
{"title":"High performance Cu interconnects with low-k BCB-polymers by plasma-enhanced monomer-vapor polymerization (PE-MVP) method","authors":"J. Kawahara, A. Nakano, S. Saito, K. Kinoshita, T. Onodera, Y. Hayashi","doi":"10.1109/VLSIT.1999.799332","DOIUrl":"https://doi.org/10.1109/VLSIT.1999.799332","url":null,"abstract":"A new plasma-enhanced organic monomer-vapor polymerization (PE-MVP) method is developed for deposition of divinyl siloxane bis-benzocyclobutene (DVS-BCB) polymer films with low dielectric constant, k=2.7. The PE-MVP method eliminates polymer oxidation of DVS-BCB during polymerization, improving the thermal stability. By combining the MOCVD-Cu technique with the PE-MVP, narrow-pitch Cu/BCB damascene lines reveal a 35% reduction in the line capacitance compared to Cu/SiO/sub 2/ lines, while the interline leakage current is kept as low as 5/spl times/10/sup -9/ A/cm/sup 2/.","PeriodicalId":171010,"journal":{"name":"1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122686502","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A concept of gate oxide lifetime limited by "B-mode" stress induced leakage currents in direct tunneling regime 直接隧穿状态下b模应力诱发泄漏电流限制栅氧化物寿命的概念
K. Okada, H. Kubo, A. Ishinaga, K. Yoneda
{"title":"A concept of gate oxide lifetime limited by \"B-mode\" stress induced leakage currents in direct tunneling regime","authors":"K. Okada, H. Kubo, A. Ishinaga, K. Yoneda","doi":"10.1109/VLSIT.1999.799338","DOIUrl":"https://doi.org/10.1109/VLSIT.1999.799338","url":null,"abstract":"To realize further advances in MOS ULSIs, thin gate oxides in the direct tunneling regime (<3 nm) are strongly required. In this regime, the most important issue is the soft breakdown (SBD) (Depas et al., 1996) which induces the \"B-mode\" stress induced leakage current (SILC) (Okada et al., 1994 and 1998; Okada and Kawasaki, 1995; Okada, 1997). Although Weir et al. (1997) reported that the SBD induces no significant degradation to a device, Wu et al. (1998) have recently reported that the oxide breakdown immediately leads to device failure for submicron short-channel-length devices, regardless of the SBD or the hard breakdown (HBD). These reports raise controversy on how to define the oxide lifetime in this regime. Needless to say, this problem also influences on the scaling limit of silicon dioxides as the gate dielectrics. This must be discussed from the perspective of the following two aspects: (i) oxide lifetime (reliability) (Stathis and DiMaria, 1998) and (ii) chip-level off-leakage current (standby power) due to the direct tunneling current (Lo et al., 1997; Timp et al, 1998). In this paper, we studied the degradation behaviour of 2.4 nm-thick thermal oxides before and after SBD. It was revealed that the limiting factor of the oxide lifetime is no longer the SBD nor HBD but the B-mode SILC in plural transistors induced by plural SBD.","PeriodicalId":171010,"journal":{"name":"1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122103816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
Work function controlled metal gate electrode on ultrathin gate insulators 超薄栅极绝缘子上的功函数控制金属栅极
K. Nakajima, Y. Akasaka, M. Kaneko, M. Tamaoki, Y. Yamada, T. Shimizu, Y. Ozawa, K. Suguro
{"title":"Work function controlled metal gate electrode on ultrathin gate insulators","authors":"K. Nakajima, Y. Akasaka, M. Kaneko, M. Tamaoki, Y. Yamada, T. Shimizu, Y. Ozawa, K. Suguro","doi":"10.1109/VLSIT.1999.799357","DOIUrl":"https://doi.org/10.1109/VLSIT.1999.799357","url":null,"abstract":"We investigated MOS characteristics of metal gate electrodes on ultrathin gate oxide. Gate leakage currents of sputtered TiN and WN/sub x/ electrodes were found to be much higher than that of CVD TiN electrodes due to metal penetration during sputtering. Moreover, the deviation of crystal orientation of the TiN was found to affect the flat band voltage. The CVD TiN film was found to be formed with highly preferred orientation and to show very stable MOS characteristics, even on 2 nm gate oxide.","PeriodicalId":171010,"journal":{"name":"1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125905432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信