{"title":"A self-aligned split-gate flash EEPROM cell with 3-D pillar structure","authors":"F. Hayashi, J. Plummer","doi":"10.1109/VLSIT.1999.799353","DOIUrl":"https://doi.org/10.1109/VLSIT.1999.799353","url":null,"abstract":"A novel 3D memory cell has been proposed for high density future generation flash EEPROMs. A self-aligned split-gate (SASG) structure, minimizing the split-gate length, has been implemented in a pillar-shape cell with high scalability over the tunnel oxide scaling limitation. This cell technology allows an ideal split-gate cell size of 6F/sup 2/. Good programming and erase characteristics have been obtained and over-erasing has been suppressed down to a 0.1 /spl mu/m split-gate length in experimental devices.","PeriodicalId":171010,"journal":{"name":"1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131603034","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Y. Tseng, W.M. Huang, M. Mendicino, P. Welch, V. Ilderem, J. Woo
{"title":"Minimizing body instability in deep sub-micron SOI MOSFETs for sub-1 V RF applications","authors":"Y. Tseng, W.M. Huang, M. Mendicino, P. Welch, V. Ilderem, J. Woo","doi":"10.1109/VLSIT.1999.799323","DOIUrl":"https://doi.org/10.1109/VLSIT.1999.799323","url":null,"abstract":"We report an extensive study on the SOI body instability and the noise constraint dependence on device scaling for sub-1 V RF SOI CMOS applications. Also, the device parameters associated with these issues are addressed.","PeriodicalId":171010,"journal":{"name":"1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325)","volume":"220 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123094421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Kawahara, A. Nakano, S. Saito, K. Kinoshita, T. Onodera, Y. Hayashi
{"title":"High performance Cu interconnects with low-k BCB-polymers by plasma-enhanced monomer-vapor polymerization (PE-MVP) method","authors":"J. Kawahara, A. Nakano, S. Saito, K. Kinoshita, T. Onodera, Y. Hayashi","doi":"10.1109/VLSIT.1999.799332","DOIUrl":"https://doi.org/10.1109/VLSIT.1999.799332","url":null,"abstract":"A new plasma-enhanced organic monomer-vapor polymerization (PE-MVP) method is developed for deposition of divinyl siloxane bis-benzocyclobutene (DVS-BCB) polymer films with low dielectric constant, k=2.7. The PE-MVP method eliminates polymer oxidation of DVS-BCB during polymerization, improving the thermal stability. By combining the MOCVD-Cu technique with the PE-MVP, narrow-pitch Cu/BCB damascene lines reveal a 35% reduction in the line capacitance compared to Cu/SiO/sub 2/ lines, while the interline leakage current is kept as low as 5/spl times/10/sup -9/ A/cm/sup 2/.","PeriodicalId":171010,"journal":{"name":"1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122686502","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A concept of gate oxide lifetime limited by \"B-mode\" stress induced leakage currents in direct tunneling regime","authors":"K. Okada, H. Kubo, A. Ishinaga, K. Yoneda","doi":"10.1109/VLSIT.1999.799338","DOIUrl":"https://doi.org/10.1109/VLSIT.1999.799338","url":null,"abstract":"To realize further advances in MOS ULSIs, thin gate oxides in the direct tunneling regime (<3 nm) are strongly required. In this regime, the most important issue is the soft breakdown (SBD) (Depas et al., 1996) which induces the \"B-mode\" stress induced leakage current (SILC) (Okada et al., 1994 and 1998; Okada and Kawasaki, 1995; Okada, 1997). Although Weir et al. (1997) reported that the SBD induces no significant degradation to a device, Wu et al. (1998) have recently reported that the oxide breakdown immediately leads to device failure for submicron short-channel-length devices, regardless of the SBD or the hard breakdown (HBD). These reports raise controversy on how to define the oxide lifetime in this regime. Needless to say, this problem also influences on the scaling limit of silicon dioxides as the gate dielectrics. This must be discussed from the perspective of the following two aspects: (i) oxide lifetime (reliability) (Stathis and DiMaria, 1998) and (ii) chip-level off-leakage current (standby power) due to the direct tunneling current (Lo et al., 1997; Timp et al, 1998). In this paper, we studied the degradation behaviour of 2.4 nm-thick thermal oxides before and after SBD. It was revealed that the limiting factor of the oxide lifetime is no longer the SBD nor HBD but the B-mode SILC in plural transistors induced by plural SBD.","PeriodicalId":171010,"journal":{"name":"1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122103816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Nakajima, Y. Akasaka, M. Kaneko, M. Tamaoki, Y. Yamada, T. Shimizu, Y. Ozawa, K. Suguro
{"title":"Work function controlled metal gate electrode on ultrathin gate insulators","authors":"K. Nakajima, Y. Akasaka, M. Kaneko, M. Tamaoki, Y. Yamada, T. Shimizu, Y. Ozawa, K. Suguro","doi":"10.1109/VLSIT.1999.799357","DOIUrl":"https://doi.org/10.1109/VLSIT.1999.799357","url":null,"abstract":"We investigated MOS characteristics of metal gate electrodes on ultrathin gate oxide. Gate leakage currents of sputtered TiN and WN/sub x/ electrodes were found to be much higher than that of CVD TiN electrodes due to metal penetration during sputtering. Moreover, the deviation of crystal orientation of the TiN was found to affect the flat band voltage. The CVD TiN film was found to be formed with highly preferred orientation and to show very stable MOS characteristics, even on 2 nm gate oxide.","PeriodicalId":171010,"journal":{"name":"1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125905432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}