H. Horii, Byoung Taek Lee, Han Jin Lim, Suk Ho Joo, Chang Seok Kang, Cha Young Yoo, Hong Bae Park, Wan Don Kim, Sang In Lee, Moon Yong Lee
{"title":"A self-aligned stacked capacitor using novel Pt electroplating method for 1 Gbit DRAMs and beyond","authors":"H. Horii, Byoung Taek Lee, Han Jin Lim, Suk Ho Joo, Chang Seok Kang, Cha Young Yoo, Hong Bae Park, Wan Don Kim, Sang In Lee, Moon Yong Lee","doi":"10.1109/VLSIT.1999.799361","DOIUrl":"https://doi.org/10.1109/VLSIT.1999.799361","url":null,"abstract":"We first developed a novel self-aligned electroplating process to fabricate Pt electrodes for integrated high-dielectric capacitors. Electroplated Pt filled 120 nm-wide buried contact (BC) holes (aspect ratio 2:1). Pt pillars of 210 nm diameter and 650 nm height were successfully fabricated. The leakage current density of sputtered BST capacitors using electroplated bottom Pt was less than 200 nA/cm/sup 2/ at /spl plusmn/1.5 V. The oxide-equivalent thickness T/sub oxeq/ and dissipation factor of 40 nm-thick BST films were 0.70 nm and 0.0080 at 0 V, respectively.","PeriodicalId":171010,"journal":{"name":"1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115092456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. Kimijima, B. Evans, B. Acker, J. Bloom, H. Mabuchi, Dim-Lee Kwong, E. Morifuji, T. Yoshitomi, H. Momose, M. Kinugawa, H. Iwai
{"title":"Improvement of 1/f noise by using VHP (vertical high pressure) oxynitride gate insulator for deep-sub micron RF and analog CMOS","authors":"H. Kimijima, B. Evans, B. Acker, J. Bloom, H. Mabuchi, Dim-Lee Kwong, E. Morifuji, T. Yoshitomi, H. Momose, M. Kinugawa, H. Iwai","doi":"10.1109/VLSIT.1999.799372","DOIUrl":"https://doi.org/10.1109/VLSIT.1999.799372","url":null,"abstract":"The 1/f noise in MOSFETs using VHP (vertical high pressure) oxynitride gate insulator was studied. The 1/f noise is degraded by conventional oxynitride gate insulators. It was found that 1/f noise can be improved by using the VHP oxynitride gate insulator.","PeriodicalId":171010,"journal":{"name":"1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116474368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Ajmera, J. Sleight, F. Assaderaghi, R. Bolam, A. Bryant, M. Coffey, H. Hovel, J. Lasky, E. Leobandung, W. Rausch, D. Sadana, D. Schepis, L. Wagner, K. Wu, B. Davari, G. Shahidi
{"title":"A 0.22 /spl mu/m CMOS-SOI technology with a Cu BEOL","authors":"A. Ajmera, J. Sleight, F. Assaderaghi, R. Bolam, A. Bryant, M. Coffey, H. Hovel, J. Lasky, E. Leobandung, W. Rausch, D. Sadana, D. Schepis, L. Wagner, K. Wu, B. Davari, G. Shahidi","doi":"10.1109/VLSIT.1999.799317","DOIUrl":"https://doi.org/10.1109/VLSIT.1999.799317","url":null,"abstract":"A 0.22 /spl mu/m CMOS on SOI technology, using a nonfully depleted device, is developed. This technology uses the same gate lithography and metallization as a comparable bulk technology, but offers a 20-35% higher performance at the chip level. Furthermore, it offers the complete device and circuit elements used in bulk CMOS (low V/sub T/ device, ESD diode, and decoupling capacitance). This technology was applied to a 64 b RISC processor.","PeriodicalId":171010,"journal":{"name":"1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325)","volume":"246 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122122420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"0.1 /spl mu/m CMOS with shallow and steep source/drain extensions fabricated by using rapid vapor-phase doping (RVD)","authors":"T. Uchino, Y. Kiyota, T. Shiba","doi":"10.1109/VLSIT.1999.799356","DOIUrl":"https://doi.org/10.1109/VLSIT.1999.799356","url":null,"abstract":"We have developed an advanced 0.1 /spl mu/m CMOS technology to form 39 nm deep p-type junctions with sheet resistance as low as 630 /spl Omega//sq using two techniques in combination: rapid vapor-phase doping (RVD) and solid-phase diffusion (SPD). These RVD- and SPD-devices have shown excellent short channel characteristics down to 0.1 /spl mu/m effective channel length and 40% higher maximum drain current compared with conventional devices with ion implanted source/drain extensions (SDEs), and high-speed circuit performance. We have also investigated the effect of the SDE structure on device performance. We found that a gate-extension overlap of 0.05 /spl mu/m enabled excellent DC and high-speed circuit performance in 0.1-/spl mu/m devices.","PeriodicalId":171010,"journal":{"name":"1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130104493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Substrate enhanced gate current: device design and temperature impact and disturbs in programming flash memories with negative body bias","authors":"R. Annunziata, T. Ghilardi, M. Tosi","doi":"10.1109/VLSIT.1999.799351","DOIUrl":"https://doi.org/10.1109/VLSIT.1999.799351","url":null,"abstract":"Substrate negative polarization enhances gate current in submicron MOSFETs, improving two different hot carrier mechanisms (Esseni et al., 1998): CHEI (channel hot electron injection) and CISEI (channel induced secondary electron injection) (Bude et al, 1995). This effect is of particular interest in flash memory research, because it allows low power programming. In this paper, we first identify which of the two mechanisms prevails for each bias scheme, with or without body bias. Then, we analyse experimentally the impact of some device parameters and temperature on the total gate current, identifying the different trends of CHEI and CISEI. Finally, the programming disturbs are evaluated. Substrate polarization could worsen the electrical stress of the cells which belong to the same word line or bit line of the selected one, since the substrate is shared by the whole array.","PeriodicalId":171010,"journal":{"name":"1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115516568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Nakamura, R. Suzuki, M. Fukuda, M. Kobayashi, A. Hatada
{"title":"Aluminum word line and bit line fabrication technology for COB DRAM using a polysilicon-aluminum substitute","authors":"S. Nakamura, R. Suzuki, M. Fukuda, M. Kobayashi, A. Hatada","doi":"10.1109/VLSIT.1999.799327","DOIUrl":"https://doi.org/10.1109/VLSIT.1999.799327","url":null,"abstract":"It is possible to employ the low resistance (but low melting point) material aluminum in word lines and bit lines for COB (capacitor-over-bit line) type DRAM or DRAM/logic, even though high temperature processes are adapted after word line and bit line fabrications. Aluminum successfully diffuses into 0.1-0.5 /spl mu/m width primary polysilicon lines through polysilicon vertical plugs using the polysilicon-aluminum substitute (PAS) technique (Horie et al, IEDM Tech. Dig., p. 946, 1996) after completion of all high temperature processes. This aluminum line provides enough length to create even 512 bit/line, with high purity (99% Al), large grains and low resistance.","PeriodicalId":171010,"journal":{"name":"1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325)","volume":"124 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115753330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Crowder, S. Greco, H. Ng, E. Barth, K. Beyer, G. Biery, J. Connolly, C. Dewan, R. Ferguson, X. Chen, M. Hargrove, E. Nowak, P. McLaughlin, R. Purtell, R. Logan, J. Oberschmidt, A. Ray, D. Ryan, K. Tallman, T. Wagner, V. McGahay, E. Crabbé, P. Agnello, R. Goldblatt, L. Su, B. Davari
{"title":"A 0.18 /spl mu/m high-performance logic technology","authors":"S. Crowder, S. Greco, H. Ng, E. Barth, K. Beyer, G. Biery, J. Connolly, C. Dewan, R. Ferguson, X. Chen, M. Hargrove, E. Nowak, P. McLaughlin, R. Purtell, R. Logan, J. Oberschmidt, A. Ray, D. Ryan, K. Tallman, T. Wagner, V. McGahay, E. Crabbé, P. Agnello, R. Goldblatt, L. Su, B. Davari","doi":"10.1109/VLSIT.1999.799362","DOIUrl":"https://doi.org/10.1109/VLSIT.1999.799362","url":null,"abstract":"In this paper, we describe a high-performance 0.18 /spl mu/m logic technology with dual damascene copper metallization and dense SRAM memory. Local interconnect technology allows us to fabricate SRAM cells as small as 3.84 /spl mu/m/sup 2/. We demonstrate that copper metallization continues to exhibit performance advantages over aluminum-based technologies in this generation.","PeriodicalId":171010,"journal":{"name":"1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129824481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Suppression of anomalous leakage current in tunnel oxides by fluorine implantation to realize highly reliable flash memory","authors":"M. Ushiyama, A. Satoh, H. Kume","doi":"10.1109/VLSIT.1999.799321","DOIUrl":"https://doi.org/10.1109/VLSIT.1999.799321","url":null,"abstract":"By analyzing charge retention characteristics, we found that a flash memory with a critical tunnel oxide thickness has cells with anomalous threshold voltage (V/sub th/) lowering. We proposed a model where the traps near the poly-Si gate/tunnel oxide interface generate anomalous leakage current in the voltage range of 0-1 V, and the trapping/detrapping of electrons into the traps dominates the V/sub th/ distribution. We succeeded in suppressing the anomalous leakage current of the tunnel oxide by fluorine implantation into the Si substrate.","PeriodicalId":171010,"journal":{"name":"1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130772892","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Ha, S.H. Kim, W.S. Kim, J. Ku, H. Lee, J. Park, K. Fujihara, H. Kang, M.Y. Lee
{"title":"Channel engineering for 0.2 /spl mu/m surface channel pMOSFETs using electron beam irradiation","authors":"J. Ha, S.H. Kim, W.S. Kim, J. Ku, H. Lee, J. Park, K. Fujihara, H. Kang, M.Y. Lee","doi":"10.1109/VLSIT.1999.799345","DOIUrl":"https://doi.org/10.1109/VLSIT.1999.799345","url":null,"abstract":"The electron beam (EB) irradiation process has been investigated to control the channel dopant profile of 0.2 /spl mu/m surface channel pMOSFETs for the first time. The results show that the channel dopants are redistributed along the EB-induced point defects by subsequent annealing when the EB is used to directly irradiate the pMOSFETs. As compared to the control process, EB treatment not only increases drive current by 14% but also reduces junction capacitance by 20% in pMOSFETs, despite the fact that EB treatment causes a reverse short channel effect. No degradation of the gate oxide reliability was identified for the EB treated sample.","PeriodicalId":171010,"journal":{"name":"1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116934310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. Liu, F. Baumann, A. Ghetti, H. Vuong, C. Chang, K. Cheung, J. Colonell, W. Lai, E. J. Lloyd, J. Miner, C. Pai, H. Vaidya, R. Liu, J. Clemens
{"title":"Severe thickness variation of sub-3 nm gate oxide due to Si surface faceting, poly-Si intrusion, and corner stress","authors":"C. Liu, F. Baumann, A. Ghetti, H. Vuong, C. Chang, K. Cheung, J. Colonell, W. Lai, E. J. Lloyd, J. Miner, C. Pai, H. Vaidya, R. Liu, J. Clemens","doi":"10.1109/VLSIT.1999.799347","DOIUrl":"https://doi.org/10.1109/VLSIT.1999.799347","url":null,"abstract":"In the fabrication of CMOS devices with sub-3 nm gate oxides, we have observed severe variation of the oxide thickness (t/sub ox/). For devices with 2.5 nm t/sub ox/ at the center of the channel, the physical t/sub ox/ ranges from 1.8 nm to 4.2 nm at various channel positions. This is caused by different oxide growth rates determined by the orientation and stress conditions of the local Si surface, especially at the rounded corners of the shallow-trench isolation (STI). In addition, poly-Si intrusion from the gate electrode also causes local t/sub ox/ thinning. Such severe variation of t/sub ox/ becomes the challenge of STI engineering, gate-oxide scaling and qualification.","PeriodicalId":171010,"journal":{"name":"1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132613528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}