S. Crowder, S. Greco, H. Ng, E. Barth, K. Beyer, G. Biery, J. Connolly, C. Dewan, R. Ferguson, X. Chen, M. Hargrove, E. Nowak, P. McLaughlin, R. Purtell, R. Logan, J. Oberschmidt, A. Ray, D. Ryan, K. Tallman, T. Wagner, V. McGahay, E. Crabbé, P. Agnello, R. Goldblatt, L. Su, B. Davari
{"title":"一个0.18 /spl mu/m的高性能逻辑技术","authors":"S. Crowder, S. Greco, H. Ng, E. Barth, K. Beyer, G. Biery, J. Connolly, C. Dewan, R. Ferguson, X. Chen, M. Hargrove, E. Nowak, P. McLaughlin, R. Purtell, R. Logan, J. Oberschmidt, A. Ray, D. Ryan, K. Tallman, T. Wagner, V. McGahay, E. Crabbé, P. Agnello, R. Goldblatt, L. Su, B. Davari","doi":"10.1109/VLSIT.1999.799362","DOIUrl":null,"url":null,"abstract":"In this paper, we describe a high-performance 0.18 /spl mu/m logic technology with dual damascene copper metallization and dense SRAM memory. Local interconnect technology allows us to fabricate SRAM cells as small as 3.84 /spl mu/m/sup 2/. We demonstrate that copper metallization continues to exhibit performance advantages over aluminum-based technologies in this generation.","PeriodicalId":171010,"journal":{"name":"1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"A 0.18 /spl mu/m high-performance logic technology\",\"authors\":\"S. Crowder, S. Greco, H. Ng, E. Barth, K. Beyer, G. Biery, J. Connolly, C. Dewan, R. Ferguson, X. Chen, M. Hargrove, E. Nowak, P. McLaughlin, R. Purtell, R. Logan, J. Oberschmidt, A. Ray, D. Ryan, K. Tallman, T. Wagner, V. McGahay, E. Crabbé, P. Agnello, R. Goldblatt, L. Su, B. Davari\",\"doi\":\"10.1109/VLSIT.1999.799362\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we describe a high-performance 0.18 /spl mu/m logic technology with dual damascene copper metallization and dense SRAM memory. Local interconnect technology allows us to fabricate SRAM cells as small as 3.84 /spl mu/m/sup 2/. We demonstrate that copper metallization continues to exhibit performance advantages over aluminum-based technologies in this generation.\",\"PeriodicalId\":171010,\"journal\":{\"name\":\"1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1999-06-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.1999.799362\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.1999.799362","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 0.18 /spl mu/m high-performance logic technology
In this paper, we describe a high-performance 0.18 /spl mu/m logic technology with dual damascene copper metallization and dense SRAM memory. Local interconnect technology allows us to fabricate SRAM cells as small as 3.84 /spl mu/m/sup 2/. We demonstrate that copper metallization continues to exhibit performance advantages over aluminum-based technologies in this generation.