{"title":"用快速气相掺杂(RVD)制备了0.1 /spl μ m源极和极陡源极扩展的CMOS","authors":"T. Uchino, Y. Kiyota, T. Shiba","doi":"10.1109/VLSIT.1999.799356","DOIUrl":null,"url":null,"abstract":"We have developed an advanced 0.1 /spl mu/m CMOS technology to form 39 nm deep p-type junctions with sheet resistance as low as 630 /spl Omega//sq using two techniques in combination: rapid vapor-phase doping (RVD) and solid-phase diffusion (SPD). These RVD- and SPD-devices have shown excellent short channel characteristics down to 0.1 /spl mu/m effective channel length and 40% higher maximum drain current compared with conventional devices with ion implanted source/drain extensions (SDEs), and high-speed circuit performance. We have also investigated the effect of the SDE structure on device performance. We found that a gate-extension overlap of 0.05 /spl mu/m enabled excellent DC and high-speed circuit performance in 0.1-/spl mu/m devices.","PeriodicalId":171010,"journal":{"name":"1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"0.1 /spl mu/m CMOS with shallow and steep source/drain extensions fabricated by using rapid vapor-phase doping (RVD)\",\"authors\":\"T. Uchino, Y. Kiyota, T. Shiba\",\"doi\":\"10.1109/VLSIT.1999.799356\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We have developed an advanced 0.1 /spl mu/m CMOS technology to form 39 nm deep p-type junctions with sheet resistance as low as 630 /spl Omega//sq using two techniques in combination: rapid vapor-phase doping (RVD) and solid-phase diffusion (SPD). These RVD- and SPD-devices have shown excellent short channel characteristics down to 0.1 /spl mu/m effective channel length and 40% higher maximum drain current compared with conventional devices with ion implanted source/drain extensions (SDEs), and high-speed circuit performance. We have also investigated the effect of the SDE structure on device performance. We found that a gate-extension overlap of 0.05 /spl mu/m enabled excellent DC and high-speed circuit performance in 0.1-/spl mu/m devices.\",\"PeriodicalId\":171010,\"journal\":{\"name\":\"1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1999-06-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.1999.799356\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.1999.799356","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
0.1 /spl mu/m CMOS with shallow and steep source/drain extensions fabricated by using rapid vapor-phase doping (RVD)
We have developed an advanced 0.1 /spl mu/m CMOS technology to form 39 nm deep p-type junctions with sheet resistance as low as 630 /spl Omega//sq using two techniques in combination: rapid vapor-phase doping (RVD) and solid-phase diffusion (SPD). These RVD- and SPD-devices have shown excellent short channel characteristics down to 0.1 /spl mu/m effective channel length and 40% higher maximum drain current compared with conventional devices with ion implanted source/drain extensions (SDEs), and high-speed circuit performance. We have also investigated the effect of the SDE structure on device performance. We found that a gate-extension overlap of 0.05 /spl mu/m enabled excellent DC and high-speed circuit performance in 0.1-/spl mu/m devices.